From: stroese <stroese>
Date: Tue, 3 May 2005 06:12:20 +0000 (+0000)
Subject: * Patch by Matthias Fuchs, 03 May 2005:
X-Git-Url: http://git.dujemihanovic.xyz/img/sics.gif?a=commitdiff_plain;h=81b83c9ecc5dc9044d805221a44f2eec82b8d57d;p=u-boot.git

* Patch by Matthias Fuchs, 03 May 2005:
  Added missing variable declaration in cmd_nand.c
  Modified CFG_PCI_PTM1MS in configs/PLU405.h to map 128MB ram
---

diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index 6057dd1a2a..dc268c85b1 100644
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -1218,6 +1218,8 @@ static int nand_write_page (struct nand_chip *nand,
 	}
 	if (nand->bus16) {
 		for (i = 0; i < nand->oobsize; i += 2) {
+			u16 val;
+
 			val = READ_NAND (nand->IO_ADDR);
 			nand->data_buf[i] = val & 0xff;
 			nand->data_buf[i + 1] = val >> 8;
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index 73a7885435..7ee95df11f 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -212,7 +212,7 @@
 #define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
 #define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 #define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1MS  0xf8000001      /* 128MB, enable hard-wired to 1 */
 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 #define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
 #define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */