From: Marek Vasut <marek.vasut+renesas@mailbox.org>
Date: Sat, 13 Jul 2024 13:19:25 +0000 (+0200)
Subject: mips: Remove duplicate newlines
X-Git-Url: http://git.dujemihanovic.xyz/img/sics.gif?a=commitdiff_plain;h=76964e3f6dd1ec014c765f67844c9bc201749ef2;p=u-boot.git

mips: Remove duplicate newlines

Drop all duplicate newlines. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---

diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 3774acaadc..4acc439ccf 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -485,7 +485,6 @@ BUILDSTRING(q, u64)
 #define outsq outsq
 #endif
 
-
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 #define mmiowb() wmb()
 #else
diff --git a/arch/mips/include/asm/isa-rev.h b/arch/mips/include/asm/isa-rev.h
index 683ea3454d..8afa6aefc5 100644
--- a/arch/mips/include/asm/isa-rev.h
+++ b/arch/mips/include/asm/isa-rev.h
@@ -20,5 +20,4 @@
 #define MIPS_ISA_REV 0
 #endif
 
-
 #endif /* __MIPS_ASM_ISA_REV_H__ */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 3db3965fcf..d02b1e50bd 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -125,7 +125,6 @@
  */
 #define CP0_TX39_CACHE	$7
 
-
 /* Generic EntryLo bit definitions */
 #define ENTRYLO_G		(_ULCAST_(1) << 0)
 #define ENTRYLO_V		(_ULCAST_(1) << 1)
@@ -987,7 +986,6 @@
 #define CP1_FENR	$28
 #define CP1_STATUS	$31
 
-
 /*
  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
  */
@@ -1102,7 +1100,6 @@
 #define FPU_CSR_RU	0x2	/* towards +Infinity */
 #define FPU_CSR_RD	0x3	/* towards -Infinity */
 
-
 #ifndef __ASSEMBLY__
 
 /*
@@ -1261,7 +1258,6 @@ static inline void tlbinvf(void)
 		".set pop");
 }
 
-
 /*
  * Functions to access the R10000 performance counters.	 These are basically
  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
@@ -1307,7 +1303,6 @@ do {								\
 	: "r" (val), "i" (counter));				\
 } while (0)
 
-
 /*
  * Macros to access the system control coprocessor
  */
@@ -2403,7 +2398,6 @@ do {									\
 	mfhi3;								\
 })
 
-
 #define mtlo0(x)							\
 ({									\
 	__asm__(							\
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index 481d2ef6c2..2dacdbbcdb 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -7,7 +7,6 @@
 #ifndef _ASM_PGTABLE_BITS_H
 #define _ASM_PGTABLE_BITS_H
 
-
 /*
  * Note that we shift the lower 32bits of each EntryLo[01] entry
  * 6 bits to the left. That way we can convert the PFN into the
@@ -189,7 +188,6 @@
  *   32-bit, R2 or later:       CCC D V G RI/R XI M A W P
  */
 
-
 #ifndef __ASSEMBLY__
 /*
  * pte_to_entrylo converts a page table entry (PTE) into a Mips
diff --git a/arch/mips/mach-ath79/qca953x/clk.c b/arch/mips/mach-ath79/qca953x/clk.c
index 379085f1ff..e9a80c6f12 100644
--- a/arch/mips/mach-ath79/qca953x/clk.c
+++ b/arch/mips/mach-ath79/qca953x/clk.c
@@ -61,7 +61,6 @@ int get_clocks(void)
 			& QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK) + 1;
 	gd->cpu_clk = pll / div;
 
-
 	val = readl(regs + QCA953X_PLL_DDR_CONFIG_REG);
 	/* VCOOUT = XTAL * DIV_INT */
 	div = (val >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT)
diff --git a/arch/mips/mach-octeon/include/mangle-port.h b/arch/mips/mach-octeon/include/mangle-port.h
index 7e95dcef5a..554bdc55cf 100644
--- a/arch/mips/mach-octeon/include/mangle-port.h
+++ b/arch/mips/mach-octeon/include/mangle-port.h
@@ -43,7 +43,6 @@ static inline bool __should_swizzle_addr(u64 p)
 
 #endif /* __BIG_ENDIAN */
 
-
 # define ioswabb(a, x)		(x)
 # define __mem_ioswabb(a, x)	(x)
 # define ioswabw(a, x)		(__should_swizzle_bits(a) ? le16_to_cpu(x) : x)