From: William Zhang Date: Mon, 22 Aug 2022 18:49:06 +0000 (-0700) Subject: arm: bcmbca: add bcm6855 SoC support under CONFIG_ARCH_BCMBCA X-Git-Url: http://git.dujemihanovic.xyz/img/sics.gif?a=commitdiff_plain;h=62c0ae40bb7c2a8c520374fe94c74d8192af0a1c;p=u-boot.git arm: bcmbca: add bcm6855 SoC support under CONFIG_ARCH_BCMBCA BCM6855 is a Broadcom ARM A7 based PON Gateway SoC. It is part of the BCA (Broadband Carrier Access origin) chipset family. Like other broadband SoC, this patch adds it under CONFIG_BCM6855 chip config and CONFIG_ARCH_BCMBCA platform config. This initial support includes a bare-bone implementation and dts with CPU subsystem, memory and ARM PL101 uart. This SoC is supported in the linux-next git repository so the dts and dtsi files are copied from linux. The u-boot image can be loaded from flash or network to the entry point address in the memory and boot from there to the console. Signed-off-by: William Zhang Reviewed-by: Philippe Reynes --- diff --git a/MAINTAINERS b/MAINTAINERS index e86ffc0e3f..03fc6c5c28 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -229,6 +229,7 @@ N: bcm[9]?63178 N: bcm[9]?6756 N: bcm[9]?6813 N: bcm[9]?6846 +N: bcm[9]?6855 N: bcm[9]?6856 N: bcm[9]?6858 N: bcm[9]?6878 diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 546a46008c..68630a7c9a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1193,6 +1193,8 @@ dtb-$(CONFIG_BCM6813) += \ bcm96813.dtb dtb-$(CONFIG_BCM6846) += \ bcm96846.dtb +dtb-$(CONFIG_BCM6855) += \ + bcm96855.dtb dtb-$(CONFIG_BCM6856) += \ bcm96856.dtb \ bcm968360bg.dtb diff --git a/arch/arm/dts/bcm6855.dtsi b/arch/arm/dts/bcm6855.dtsi new file mode 100644 index 0000000000..620f51aee1 --- /dev/null +++ b/arch/arm/dts/bcm6855.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include +#include + +/ { + compatible = "brcm,bcm6855", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + ; + interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = ; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/bcm96855.dts b/arch/arm/dts/bcm96855.dts new file mode 100644 index 0000000000..e4e740c73e --- /dev/null +++ b/arch/arm/dts/bcm96855.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6855.dtsi" + +/ { + model = "Broadcom BCM96855 Reference Board"; + compatible = "brcm,bcm96855", "brcm,bcm6855", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/mach-bcmbca/Kconfig b/arch/arm/mach-bcmbca/Kconfig index 5b977734df..27b243cbc3 100644 --- a/arch/arm/mach-bcmbca/Kconfig +++ b/arch/arm/mach-bcmbca/Kconfig @@ -83,6 +83,16 @@ config BCM6846 select DM_SERIAL select BCM6345_SERIAL +config BCM6855 + bool "Support for Broadcom 6855 Family" + select SYS_ARCH_TIMER + select CPU_V7A + select DM_SERIAL + select PL01X_SERIAL + help + Broadcom BCM6855 is a triple core Cortex A7 based xPON Gateway + SoC. This SoC family includes BCM6855x, BCM68252 and BCM6753. + config BCM6856 bool "Support for Broadcom 6856 Family" select ARM64 @@ -121,6 +131,7 @@ source "arch/arm/mach-bcmbca/bcm63178/Kconfig" source "arch/arm/mach-bcmbca/bcm6756/Kconfig" source "arch/arm/mach-bcmbca/bcm6813/Kconfig" source "arch/arm/mach-bcmbca/bcm6846/Kconfig" +source "arch/arm/mach-bcmbca/bcm6855/Kconfig" source "arch/arm/mach-bcmbca/bcm6856/Kconfig" source "arch/arm/mach-bcmbca/bcm6858/Kconfig" source "arch/arm/mach-bcmbca/bcm6878/Kconfig" diff --git a/arch/arm/mach-bcmbca/Makefile b/arch/arm/mach-bcmbca/Makefile index c068094174..7de9450e19 100644 --- a/arch/arm/mach-bcmbca/Makefile +++ b/arch/arm/mach-bcmbca/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_BCM63178) += bcm63178/ obj-$(CONFIG_BCM6756) += bcm6756/ obj-$(CONFIG_BCM6813) += bcm6813/ obj-$(CONFIG_BCM6846) += bcm6846/ +obj-$(CONFIG_BCM6855) += bcm6855/ obj-$(CONFIG_BCM6856) += bcm6856/ obj-$(CONFIG_BCM6858) += bcm6858/ obj-$(CONFIG_BCM6878) += bcm6878/ diff --git a/arch/arm/mach-bcmbca/bcm6855/Kconfig b/arch/arm/mach-bcmbca/bcm6855/Kconfig new file mode 100644 index 0000000000..78087c7dd5 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm6855/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# + +if BCM6855 + +config TARGET_BCM96855 + bool "Broadcom 6855 Reference Board" + depends on ARCH_BCMBCA + +config SYS_SOC + default "bcm6855" + +source "board/broadcom/bcmbca/Kconfig" + +endif diff --git a/arch/arm/mach-bcmbca/bcm6855/Makefile b/arch/arm/mach-bcmbca/bcm6855/Makefile new file mode 100644 index 0000000000..beb979af75 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm6855/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# +obj- += dummy.o diff --git a/board/broadcom/bcmbca/Kconfig b/board/broadcom/bcmbca/Kconfig index 7da9e954d4..5903a6a786 100644 --- a/board/broadcom/bcmbca/Kconfig +++ b/board/broadcom/bcmbca/Kconfig @@ -86,6 +86,13 @@ config SYS_CONFIG_NAME endif +if TARGET_BCM96855 + +config SYS_CONFIG_NAME + default "bcm96855" + +endif + if TARGET_BCM96856 config SYS_CONFIG_NAME diff --git a/configs/bcm96855_defconfig b/configs/bcm96855_defconfig new file mode 100644 index 0000000000..223c0a139b --- /dev/null +++ b/configs/bcm96855_defconfig @@ -0,0 +1,23 @@ +CONFIG_ARM=y +CONFIG_COUNTER_FREQUENCY=50000000 +CONFIG_ARCH_BCMBCA=y +CONFIG_SYS_TEXT_BASE=0x01000000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_BCM6855=y +CONFIG_TARGET_BCM96855=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="bcm96855" +CONFIG_IDENT_STRING=" Broadcom BCM6855" +CONFIG_SYS_LOAD_ADDR=0x01000000 +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x4000000 +CONFIG_CMD_CACHE=y +CONFIG_OF_EMBED=y +CONFIG_CLK=y diff --git a/include/configs/bcm96855.h b/include/configs/bcm96855.h new file mode 100644 index 0000000000..6e420f2c66 --- /dev/null +++ b/include/configs/bcm96855.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2022 Broadcom Ltd. + */ + +#ifndef __BCM96855_H +#define __BCM96855_H + +#define CONFIG_SYS_SDRAM_BASE 0x00000000 + +#endif