From: Marek Vasut Date: Sun, 17 Sep 2023 14:11:41 +0000 (+0200) Subject: clk: renesas: Synchronize R8A774E1 RZ/G2H clock tables with Linux 6.5.3 X-Git-Url: http://git.dujemihanovic.xyz/img/sics.gif?a=commitdiff_plain;h=610b078b33835236178b396b899e38b17205f14e;p=u-boot.git clk: renesas: Synchronize R8A774E1 RZ/G2H clock tables with Linux 6.5.3 Synchronize R8A774E1 RZ/G2H clock tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut --- diff --git a/drivers/clk/renesas/r8a774e1-cpg-mssr.c b/drivers/clk/renesas/r8a774e1-cpg-mssr.c index 617fa769dc..28d8a8832a 100644 --- a/drivers/clk/renesas/r8a774e1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774e1-cpg-mssr.c @@ -48,7 +48,7 @@ enum clk_ids { MOD_CLK_BASE }; -static const struct cpg_core_clk r8a774e1_core_clks[] = { +static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), DEF_INPUT("extalr", CLK_EXTALR), @@ -123,7 +123,7 @@ static const struct cpg_core_clk r8a774e1_core_clks[] = { DEF_BASE("r", R8A774E1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), }; -static const struct mssr_mod_clk r8a774e1_mod_clks[] = { +static const struct mssr_mod_clk r8a774e1_mod_clks[] __initconst = { DEF_MOD("fdp1-1", 118, R8A774E1_CLK_S0D1), DEF_MOD("fdp1-0", 119, R8A774E1_CLK_S0D1), DEF_MOD("tmu4", 121, R8A774E1_CLK_S0D6), @@ -286,7 +286,7 @@ static const struct mssr_mod_clk r8a774e1_mod_clks[] = { (((md) & BIT(19)) >> 18) | \ (((md) & BIT(17)) >> 17)) -static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = { +static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */ { 1, 192, 1, 192, 1, 16, }, { 1, 192, 1, 128, 1, 16, },