From: Marek Vasut Date: Mon, 9 Aug 2021 12:06:04 +0000 (+0200) Subject: ARM: dts: stm32: Reduce DHCOR SPI NOR frequency to 50 MHz X-Git-Url: http://git.dujemihanovic.xyz/img/sics.gif?a=commitdiff_plain;h=59f6eb477e053355718fa25b3bce956991f016b8;p=u-boot.git ARM: dts: stm32: Reduce DHCOR SPI NOR frequency to 50 MHz The SPI NOR is a bit further away from the SoC on DHCOR than on DHCOM, which causes additional signal delay. At 108 MHz, this delay triggers a sporadic issue where the first bit of RX data is not received by the QSPI controller. There are two options of addressing this problem, either by using the DLYB block to compensate the extra delay, or by reducing the QSPI bus clock frequency. The former requires calibration and that is overly complex for SPL, so opt for the second option. This incurs 20ms delay during boot, when SPL loads U-Boot to DRAM. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrice Chotard --- diff --git a/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi index 64299df816..94cf80dbed 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-io3v3.dtsi @@ -198,7 +198,7 @@ compatible = "jedec,spi-nor"; reg = <0>; spi-rx-bus-width = <4>; - spi-max-frequency = <108000000>; + spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; };