From: Suneel Garapati <sgarapati@marvell.com>
Date: Sun, 20 Oct 2019 00:48:25 +0000 (-0700)
Subject: ata: ahci: Add BAR index quirk for Cavium PCI SATA device
X-Git-Url: http://git.dujemihanovic.xyz/img/sics.gif?a=commitdiff_plain;h=3f6f0cd8fd809287838153d355311f1499040758;p=u-boot.git

ata: ahci: Add BAR index quirk for Cavium PCI SATA device

For SATA controller found on OcteonTX SoC's, use non-standard PCI BAR0
instead of BAR5.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---

diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 47cdea1f58..22bc0d3b10 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -1198,10 +1198,25 @@ int ahci_probe_scsi(struct udevice *ahci_dev, ulong base)
 int ahci_probe_scsi_pci(struct udevice *ahci_dev)
 {
 	ulong base;
+	u16 vendor, device;
 
 	base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5,
 				     PCI_REGION_MEM);
 
+	/*
+	 * Note:
+	 * Right now, we have only one quirk here, which is not enough to
+	 * introduce a new Kconfig option to select this. Once we have more
+	 * quirks in this AHCI code, we should add a Kconfig option for
+	 * this though.
+	 */
+	dm_pci_read_config16(ahci_dev, PCI_VENDOR_ID, &vendor);
+	dm_pci_read_config16(ahci_dev, PCI_DEVICE_ID, &device);
+
+	if (vendor == PCI_VENDOR_ID_CAVIUM &&
+	    device == PCI_DEVICE_ID_CAVIUM_SATA)
+		base = (uintptr_t)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_0,
+						 PCI_REGION_MEM);
 	return ahci_probe_scsi(ahci_dev, base);
 }
 #endif