From: Tom Rini <trini@konsulko.com>
Date: Mon, 15 Mar 2021 16:15:38 +0000 (-0400)
Subject: Merge tag 'v2021.04-rc4' into next
X-Git-Tag: v2025.01-rc5-pxa1908~1941^2~8
X-Git-Url: http://git.dujemihanovic.xyz/img/sics.gif?a=commitdiff_plain;h=22fc991dafee0142fc6bf621e7bd558bd58020b4;p=u-boot.git

Merge tag 'v2021.04-rc4' into next

Prepare v2021.04-rc4
---

22fc991dafee0142fc6bf621e7bd558bd58020b4
diff --cc arch/arm/mach-stm32mp/cpu.c
index d332f5aecd,bc2db535be..897ec13ad8
--- a/arch/arm/mach-stm32mp/cpu.c
+++ b/arch/arm/mach-stm32mp/cpu.c
@@@ -252,11 -223,22 +252,13 @@@ static void early_enable_caches(void
  	if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
  		return;
  
- 	gd->arch.tlb_size = PGTABLE_SIZE;
- 	gd->arch.tlb_addr = (unsigned long)&early_tlb;
+ 	if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) {
+ 		gd->arch.tlb_size = PGTABLE_SIZE;
+ 		gd->arch.tlb_addr = (unsigned long)&early_tlb;
+ 	}
  
 +	/* enable MMU (default configuration) */
  	dcache_enable();
 -
 -	if (IS_ENABLED(CONFIG_SPL_BUILD))
 -		mmu_set_region_dcache_behaviour(
 -			ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE),
 -			ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE),
 -			DCACHE_DEFAULT_OPTION);
 -	else
 -		mmu_set_region_dcache_behaviour(STM32_DDR_BASE,
 -						CONFIG_DDR_CACHEABLE_SIZE,
 -						DCACHE_DEFAULT_OPTION);
  }
  
  /*