From: Sean Anderson <seanga2@gmail.com>
Date: Fri, 9 Apr 2021 02:13:12 +0000 (-0400)
Subject: riscv: k210: Use AI as the parent clock of aisram, not PLL1
X-Git-Url: http://git.dujemihanovic.xyz/img/sics.gif?a=commitdiff_plain;h=2111f4e8bf09386c849a6273c3b21b6eb1a3fc3c;p=u-boot.git

riscv: k210: Use AI as the parent clock of aisram, not PLL1

Testing showed that disabling AI while leaving PLL1 enabled disabled the
aisram. This suggests that AI is a more appropriate clock for that ram
bank.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
---

diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi
index 2032f1e5c2..75e101530b 100644
--- a/arch/riscv/dts/k210.dtsi
+++ b/arch/riscv/dts/k210.dtsi
@@ -89,7 +89,7 @@
 		reg-names = "sram0", "sram1", "aisram";
 		clocks = <&sysclk K210_CLK_SRAM0>,
 			 <&sysclk K210_CLK_SRAM1>,
-			 <&sysclk K210_CLK_PLL1>;
+			 <&sysclk K210_CLK_AI>;
 		clock-names = "sram0", "sram1", "aisram";
 		u-boot,dm-pre-reloc;
 	};