From: T Karthik Reddy Date: Tue, 28 Sep 2021 06:00:27 +0000 (+0530) Subject: clk: versal: Enable only GATE type clocks X-Git-Url: http://git.dujemihanovic.xyz/img/sics.gif?a=commitdiff_plain;h=1db1acbb848ef1b10eccedb52edd6c37078bbd38;p=u-boot.git clk: versal: Enable only GATE type clocks Clocks should be enabled or disabled only if they are of GATE type clocks. If they are not of GATE type clocks, don't touch them. Signed-off-by: T Karthik Reddy Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/1632808827-6109-1-git-send-email-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek --- diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index 62523d2909..a9dd57b098 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -725,7 +725,10 @@ static int versal_clk_enable(struct clk *clk) clk_id = priv->clk[clk->id].clk_id; - return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL); + if (versal_clock_gate(clk_id)) + return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL); + + return 0; } static struct clk_ops versal_clk_ops = {