From: Kever Yang <kever.yang@rock-chips.com>
Date: Mon, 15 May 2017 12:52:16 +0000 (+0800)
Subject: rockchip: clock: rk3036: some fix according TRM
X-Git-Tag: v2025.01-rc5-pxa1908~6616^2~49
X-Git-Url: http://git.dujemihanovic.xyz/img/sics.gif?a=commitdiff_plain;h=1960b0103420a74ae5b154ed8684785036e2235b;p=u-boot.git

rockchip: clock: rk3036: some fix according TRM

- hclk/pclk_div range　should use '<=' instead of '<'
- use GPLL for pd_bus clock source
- pd_bus HCLK/PCLK clock rate should not bigger than ACLK

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3036.h b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h
index eb5eb40027..22278e11ac 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3036.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h
@@ -16,9 +16,9 @@
 #define CORE_PERI_HZ	150000000
 #define CORE_ACLK_HZ	300000000
 
-#define CPU_ACLK_HZ	150000000
-#define CPU_HCLK_HZ	300000000
-#define CPU_PCLK_HZ	300000000
+#define BUS_ACLK_HZ	148500000
+#define BUS_HCLK_HZ	148500000
+#define BUS_PCLK_HZ	74250000
 
 #define PERI_ACLK_HZ	148500000
 #define PERI_HCLK_HZ	148500000
diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c
index ce1c670be2..28652df72d 100644
--- a/drivers/clk/rockchip/clk_rk3036.c
+++ b/drivers/clk/rockchip/clk_rk3036.c
@@ -116,21 +116,21 @@ static void rkclk_init(struct rk3036_cru *cru)
 		     pclk_div << CORE_PERI_DIV_SHIFT);
 
 	/*
-	 * select apll as pd_bus clock pll source and
+	 * select apll as pd_bus bus clock source and
 	 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 	 */
-	aclk_div = APLL_HZ / CPU_ACLK_HZ - 1;
-	assert((aclk_div + 1) * CPU_ACLK_HZ == APLL_HZ && aclk_div < 0x1f);
+	aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
+	assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
 
-	pclk_div = APLL_HZ / CPU_PCLK_HZ - 1;
-	assert((pclk_div + 1) * CPU_PCLK_HZ == APLL_HZ && pclk_div < 0x7);
+	pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1;
+	assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
 
-	hclk_div = APLL_HZ / CPU_HCLK_HZ - 1;
-	assert((hclk_div + 1) * CPU_HCLK_HZ == APLL_HZ && hclk_div < 0x3);
+	hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1;
+	assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
 
 	rk_clrsetreg(&cru->cru_clksel_con[0],
 		     BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
-		     BUS_ACLK_PLL_SEL_APLL << BUS_ACLK_PLL_SEL_SHIFT |
+		     BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
 		     aclk_div << BUS_ACLK_DIV_SHIFT);
 
 	rk_clrsetreg(&cru->cru_clksel_con[1],
@@ -147,7 +147,7 @@ static void rkclk_init(struct rk3036_cru *cru)
 
 	hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
 	assert((1 << hclk_div) * PERI_HCLK_HZ ==
-		PERI_ACLK_HZ && (pclk_div < 0x4));
+		PERI_ACLK_HZ && (hclk_div < 0x4));
 
 	pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
 	assert((1 << pclk_div) * PERI_PCLK_HZ ==