From: Takahiro Kuwano Date: Tue, 15 Oct 2024 04:08:36 +0000 (+0900) Subject: mtd: spi-nor: Set ECC unit size to MTD writesize in Infineon SEMPER flashes X-Git-Url: http://git.dujemihanovic.xyz/img/sics.gif?a=commitdiff_plain;h=10e75dd0bce34134df15f2c2d9251a919f6bcdc7;p=u-boot.git mtd: spi-nor: Set ECC unit size to MTD writesize in Infineon SEMPER flashes The Infineon SEMPER NOR flash family uses 2-bit ECC by default with each ECC block being 16 bytes. Under this scheme multi-pass programming to an ECC block is not allowed. Set the writesize to make sure multi-pass programming is not attempted on the flash. Acked-by: Tudor Ambarus Signed-off-by: Takahiro Kuwano --- diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 46af9b4fe4..f5c9868bbc 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3855,6 +3855,13 @@ static void s25_late_init(struct spi_nor *nor, struct spi_nor_flash_parameter *params) { nor->setup = s25_s28_setup; + + /* + * Programming is supported only in 16-byte ECC data unit granularity. + * Byte-programming, bit-walking, or multiple program operations to the + * same ECC data unit without an erase are not allowed. + */ + params->writesize = 16; } static int s25_s28_post_bfpt_fixup(struct spi_nor *nor, @@ -4019,6 +4026,13 @@ static void s28hx_t_late_init(struct spi_nor *nor, { nor->octal_dtr_enable = spi_nor_cypress_octal_dtr_enable; nor->setup = s25_s28_setup; + + /* + * Programming is supported only in 16-byte ECC data unit granularity. + * Byte-programming, bit-walking, or multiple program operations to the + * same ECC data unit without an erase are not allowed. + */ + params->writesize = 16; } static void s28hx_t_post_sfdp_fixup(struct spi_nor *nor,