From: Tom Rini <trini@konsulko.com>
Date: Thu, 12 Oct 2023 23:03:59 +0000 (-0400)
Subject: riscv: Remove common.h usage
X-Git-Url: http://git.dujemihanovic.xyz/img/sics.gif?a=commitdiff_plain;h=0b9441ae76db88b6871adc31b7e59355286f2847;p=u-boot.git

riscv: Remove common.h usage

We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Rick Chen <rick@andestech.com>
---

diff --git a/arch/riscv/cpu/andesv5/cache.c b/arch/riscv/cpu/andesv5/cache.c
index 40d77f671c..269bb27f75 100644
--- a/arch/riscv/cpu/andesv5/cache.c
+++ b/arch/riscv/cpu/andesv5/cache.c
@@ -6,7 +6,6 @@
 
 #include <asm/csr.h>
 #include <asm/asm.h>
-#include <common.h>
 #include <cache.h>
 #include <cpu_func.h>
 #include <dm.h>
diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c
index 06e379bcb1..63bc24cdfc 100644
--- a/arch/riscv/cpu/andesv5/cpu.c
+++ b/arch/riscv/cpu/andesv5/cpu.c
@@ -5,7 +5,6 @@
  */
 
 /* CPU specific code */
-#include <common.h>
 #include <cpu_func.h>
 #include <irq_func.h>
 #include <asm/cache.h>
diff --git a/arch/riscv/cpu/andesv5/spl.c b/arch/riscv/cpu/andesv5/spl.c
index 413849043b..a13dc4095a 100644
--- a/arch/riscv/cpu/andesv5/spl.c
+++ b/arch/riscv/cpu/andesv5/spl.c
@@ -3,7 +3,6 @@
  * Copyright (C) 2023 Andes Technology Corporation
  * Rick Chen, Andes Technology Corporation <rick@andestech.com>
  */
-#include <common.h>
 #include <cpu_func.h>
 #include <hang.h>
 #include <init.h>
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index c1a9638c1a..ebd39cb41a 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -3,7 +3,6 @@
  * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
  */
 
-#include <common.h>
 #include <cpu.h>
 #include <dm.h>
 #include <dm/lists.h>
diff --git a/arch/riscv/cpu/fu540/dram.c b/arch/riscv/cpu/fu540/dram.c
index 94d8018407..7b5a3471ac 100644
--- a/arch/riscv/cpu/fu540/dram.c
+++ b/arch/riscv/cpu/fu540/dram.c
@@ -3,7 +3,6 @@
  * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
  */
 
-#include <common.h>
 #include <fdtdec.h>
 #include <init.h>
 #include <asm/global_data.h>
diff --git a/arch/riscv/cpu/fu740/dram.c b/arch/riscv/cpu/fu740/dram.c
index 8657fcd165..61f551763f 100644
--- a/arch/riscv/cpu/fu740/dram.c
+++ b/arch/riscv/cpu/fu740/dram.c
@@ -3,7 +3,6 @@
  * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
  */
 
-#include <common.h>
 #include <fdtdec.h>
 #include <init.h>
 #include <linux/sizes.h>
diff --git a/arch/riscv/cpu/generic/cpu.c b/arch/riscv/cpu/generic/cpu.c
index d78e1a3453..f13c18942f 100644
--- a/arch/riscv/cpu/generic/cpu.c
+++ b/arch/riscv/cpu/generic/cpu.c
@@ -3,7 +3,6 @@
  * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
  */
 
-#include <common.h>
 #include <irq_func.h>
 #include <asm/cache.h>
 
diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c
index 1b51bae9b6..91007c0a3d 100644
--- a/arch/riscv/cpu/generic/dram.c
+++ b/arch/riscv/cpu/generic/dram.c
@@ -3,7 +3,6 @@
  * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
  */
 
-#include <common.h>
 #include <fdtdec.h>
 #include <init.h>
 #include <asm/global_data.h>
diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c
index 1a9fa46d14..664b9b93eb 100644
--- a/arch/riscv/cpu/jh7110/dram.c
+++ b/arch/riscv/cpu/jh7110/dram.c
@@ -4,7 +4,6 @@
  * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
  */
 
-#include <common.h>
 #include <fdtdec.h>
 #include <init.h>
 #include <linux/sizes.h>
diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
index 4047b10efe..6bdf8b9c72 100644
--- a/arch/riscv/cpu/jh7110/spl.c
+++ b/arch/riscv/cpu/jh7110/spl.c
@@ -3,7 +3,6 @@
  * Copyright (C) 2022 StarFive Technology Co., Ltd.
  * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
  */
-#include <common.h>
 #include <asm/arch/eeprom.h>
 #include <asm/csr.h>
 #include <asm/sections.h>
diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S
index e40c7bd3f4..6eb3ed1d5a 100644
--- a/arch/riscv/cpu/mtrap.S
+++ b/arch/riscv/cpu/mtrap.S
@@ -11,7 +11,6 @@
  * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
  */
 
-#include <common.h>
 #include <asm/encoding.h>
 
 #ifdef CONFIG_32BIT
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 30cf674370..6cecadfac5 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -11,7 +11,6 @@
 
 #include <asm-offsets.h>
 #include <config.h>
-#include <common.h>
 #include <elf.h>
 #include <system-constants.h>
 #include <asm/encoding.h>
diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h
index c7ed920cde..393d51c6dd 100644
--- a/arch/riscv/include/asm/arch-andes/csr.h
+++ b/arch/riscv/include/asm/arch-andes/csr.h
@@ -7,6 +7,7 @@
 #define _ASM_ANDES_CSR_H
 
 #include <asm/asm.h>
+#include <linux/bitops.h>
 #include <linux/const.h>
 
 #define CSR_MCACHE_CTL 0x7ca
diff --git a/arch/riscv/include/asm/arch-jh7110/eeprom.h b/arch/riscv/include/asm/arch-jh7110/eeprom.h
index f354d5c60c..d2776d5b6c 100644
--- a/arch/riscv/include/asm/arch-jh7110/eeprom.h
+++ b/arch/riscv/include/asm/arch-jh7110/eeprom.h
@@ -7,6 +7,8 @@
 #ifndef _ASM_RISCV_EEPROM_H
 #define _ASM_RISCV_EEPROM_H
 
+#include <linux/types.h>
+
 u8 get_pcb_revision_from_eeprom(void);
 u32 get_ddr_size_from_eeprom(void);
 
diff --git a/arch/riscv/include/asm/dma-mapping.h b/arch/riscv/include/asm/dma-mapping.h
index 6ecadab41c..d0cc5d7c77 100644
--- a/arch/riscv/include/asm/dma-mapping.h
+++ b/arch/riscv/include/asm/dma-mapping.h
@@ -9,7 +9,6 @@
 #ifndef __ASM_RISCV_DMA_MAPPING_H
 #define __ASM_RISCV_DMA_MAPPING_H
 
-#include <common.h>
 #include <linux/types.h>
 #include <asm/cache.h>
 #include <cpu_func.h>
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
index 4284a332e9..ee749dd119 100644
--- a/arch/riscv/include/asm/smp.h
+++ b/arch/riscv/include/asm/smp.h
@@ -7,6 +7,8 @@
 #ifndef _ASM_RISCV_SMP_H
 #define _ASM_RISCV_SMP_H
 
+#include <linux/types.h>
+
 /**
  * struct ipi_data - Inter-processor interrupt (IPI) data structure
  *
diff --git a/arch/riscv/lib/aclint_ipi.c b/arch/riscv/lib/aclint_ipi.c
index 90b8e128cb..dcd7e5e6b3 100644
--- a/arch/riscv/lib/aclint_ipi.c
+++ b/arch/riscv/lib/aclint_ipi.c
@@ -8,7 +8,6 @@
  * associated with software and timer interrupts.
  */
 
-#include <common.h>
 #include <dm.h>
 #include <regmap.h>
 #include <syscon.h>
diff --git a/arch/riscv/lib/andes_plicsw.c b/arch/riscv/lib/andes_plicsw.c
index 6fd49e873b..6a63661312 100644
--- a/arch/riscv/lib/andes_plicsw.c
+++ b/arch/riscv/lib/andes_plicsw.c
@@ -8,7 +8,6 @@
  * similar to RISC-V PLIC.
  */
 
-#include <common.h>
 #include <dm.h>
 #include <asm/global_data.h>
 #include <dm/device-internal.h>
diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c
index 452dfcea97..875bb9a6d9 100644
--- a/arch/riscv/lib/asm-offsets.c
+++ b/arch/riscv/lib/asm-offsets.c
@@ -8,7 +8,6 @@
  * assembly language modules.
  */
 
-#include <common.h>
 #include <asm/global_data.h>
 #include <linux/kbuild.h>
 
diff --git a/arch/riscv/lib/boot.c b/arch/riscv/lib/boot.c
index 778d011f7c..03014c56dc 100644
--- a/arch/riscv/lib/boot.c
+++ b/arch/riscv/lib/boot.c
@@ -4,8 +4,7 @@
  * Rick Chen, Andes Technology Corporation <rick@andestech.com>
  */
 
-#include <common.h>
-#include <command.h>
+#include <asm/u-boot.h>
 
 unsigned long do_go_exec(ulong (*entry)(int, char * const []),
 			 int argc, char *const argv[])
diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index cc30efc904..f9e1e18ae0 100644
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -6,7 +6,6 @@
  * Rick Chen, Andes Technology Corporation <rick@andestech.com>
  */
 
-#include <common.h>
 #include <bootstage.h>
 #include <command.h>
 #include <dm.h>
diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c
index 686e699efb..c46b49eb0a 100644
--- a/arch/riscv/lib/cache.c
+++ b/arch/riscv/lib/cache.c
@@ -4,7 +4,6 @@
  * Rick Chen, Andes Technology Corporation <rick@andestech.com>
  */
 
-#include <common.h>
 #include <cpu_func.h>
 
 void invalidate_icache_all(void)
diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c
index 36c16e9be2..c658e72bd3 100644
--- a/arch/riscv/lib/fdt_fixup.c
+++ b/arch/riscv/lib/fdt_fixup.c
@@ -6,7 +6,6 @@
 
 #define LOG_CATEGORY LOGC_ARCH
 
-#include <common.h>
 #include <fdt_support.h>
 #include <log.h>
 #include <mapmem.h>
diff --git a/arch/riscv/lib/image.c b/arch/riscv/lib/image.c
index a65a5b8d17..a82f48e9a5 100644
--- a/arch/riscv/lib/image.c
+++ b/arch/riscv/lib/image.c
@@ -6,7 +6,6 @@
  * Based on arm/lib/image.c
  */
 
-#include <common.h>
 #include <image.h>
 #include <mapmem.h>
 #include <errno.h>
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index e966afa7e3..02dbcfd423 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -10,7 +10,6 @@
  */
 
 #include <linux/compat.h>
-#include <common.h>
 #include <efi_loader.h>
 #include <hang.h>
 #include <irq_func.h>
diff --git a/arch/riscv/lib/reset.c b/arch/riscv/lib/reset.c
index 8779c619cc..712e1bdb8e 100644
--- a/arch/riscv/lib/reset.c
+++ b/arch/riscv/lib/reset.c
@@ -3,7 +3,6 @@
  * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
  */
 
-#include <common.h>
 #include <command.h>
 #include <hang.h>
 
diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c
index 55a3bc3b5c..35a7d3b12f 100644
--- a/arch/riscv/lib/sbi.c
+++ b/arch/riscv/lib/sbi.c
@@ -7,7 +7,7 @@
  * Taken from Linux arch/riscv/kernel/sbi.c
  */
 
-#include <common.h>
+#include <errno.h>
 #include <asm/encoding.h>
 #include <asm/sbi.h>
 
diff --git a/arch/riscv/lib/sbi_ipi.c b/arch/riscv/lib/sbi_ipi.c
index d02e2b4c48..511d3816da 100644
--- a/arch/riscv/lib/sbi_ipi.c
+++ b/arch/riscv/lib/sbi_ipi.c
@@ -4,7 +4,6 @@
  * Lukas Auer <lukas.auer@aisec.fraunhofer.de>
  */
 
-#include <common.h>
 #include <asm/encoding.h>
 #include <asm/sbi.h>
 
diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c
index 28154878fc..39b0248c32 100644
--- a/arch/riscv/lib/sifive_cache.c
+++ b/arch/riscv/lib/sifive_cache.c
@@ -3,9 +3,9 @@
  * Copyright (C) 2021 SiFive, Inc
  */
 
-#include <common.h>
 #include <cache.h>
 #include <cpu_func.h>
+#include <log.h>
 #include <dm.h>
 
 void enable_caches(void)
diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
index f3cd8b9044..a692f065ed 100644
--- a/arch/riscv/lib/smp.c
+++ b/arch/riscv/lib/smp.c
@@ -4,7 +4,6 @@
  * Lukas Auer <lukas.auer@aisec.fraunhofer.de>
  */
 
-#include <common.h>
 #include <cpu_func.h>
 #include <dm.h>
 #include <asm/barrier.h>
diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c
index 9b242ed821..9a7a4f6ac8 100644
--- a/arch/riscv/lib/spl.c
+++ b/arch/riscv/lib/spl.c
@@ -3,7 +3,6 @@
  * Copyright (C) 2019 Fraunhofer AISEC,
  * Lukas Auer <lukas.auer@aisec.fraunhofer.de>
  */
-#include <common.h>
 #include <cpu_func.h>
 #include <hang.h>
 #include <init.h>
diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c
index d78ee403e6..772c6bf1ee 100644
--- a/board/AndesTech/ae350/ae350.c
+++ b/board/AndesTech/ae350/ae350.c
@@ -4,7 +4,7 @@
  * Rick Chen, Andes Technology Corporation <rick@andestech.com>
  */
 
-#include <common.h>
+#include <config.h>
 #include <cpu_func.h>
 #include <flash.h>
 #include <image.h>
diff --git a/board/sifive/unmatched/hifive-platform-i2c-eeprom.c b/board/sifive/unmatched/hifive-platform-i2c-eeprom.c
index c82fb5763e..d25c24b08b 100644
--- a/board/sifive/unmatched/hifive-platform-i2c-eeprom.c
+++ b/board/sifive/unmatched/hifive-platform-i2c-eeprom.c
@@ -9,7 +9,6 @@
  * Timur Tabi (timur@freescale.com)
  */
 
-#include <common.h>
 #include <command.h>
 #include <env.h>
 #include <i2c.h>
diff --git a/board/sifive/unmatched/unmatched.c b/board/sifive/unmatched/unmatched.c
index 6675548c2b..c8696270ba 100644
--- a/board/sifive/unmatched/unmatched.c
+++ b/board/sifive/unmatched/unmatched.c
@@ -6,7 +6,6 @@
  *   Pragnesh Patel <pragnesh.patel@sifive.com>
  */
 
-#include <common.h>
 #include <cpu_func.h>
 #include <dm.h>
 #include <asm/sections.h>