From: Jonas Karlman <jonas@kwiboo.se>
Date: Mon, 22 Apr 2024 06:28:40 +0000 (+0000)
Subject: clk: rockchip: rk356x: Fix set rate of SCLK_SFC clock
X-Git-Url: http://git.dujemihanovic.xyz/img/sics.gif?a=commitdiff_plain;h=0b6afc3993d92a542e328afdccaedf95b9c9c98f;p=u-boot.git

clk: rockchip: rk356x: Fix set rate of SCLK_SFC clock

The SCLK_SFC can be set to a rate of 24, 50, 75, 100, 125 or 150 MHz.

However, clk_set_rate() will fail unless one of those exact rates are
used, and with newer and updated device tree files that contain
spi-max-frequency values that does not exactly match these rates use of
SPI flash may fail.

Fix this by using the highest possible rate that exceeds or is equal to
the requested rate.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---

diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c
index 999f48ea4b..24eeca8bf2 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -1527,28 +1527,20 @@ static ulong rk3568_sfc_set_clk(struct rk3568_clk_priv *priv, ulong rate)
 	struct rk3568_cru *cru = priv->cru;
 	int src_clk;
 
-	switch (rate) {
-	case OSC_HZ:
-		src_clk = SCLK_SFC_SEL_24M;
-		break;
-	case 50 * MHz:
-		src_clk = SCLK_SFC_SEL_50M;
-		break;
-	case 75 * MHz:
-		src_clk = SCLK_SFC_SEL_75M;
-		break;
-	case 100 * MHz:
-		src_clk = SCLK_SFC_SEL_100M;
-		break;
-	case 125 * MHz:
-		src_clk = SCLK_SFC_SEL_125M;
-		break;
-	case 150 * MHz:
+	if (rate >= 150 * MHz)
 		src_clk = SCLK_SFC_SEL_150M;
-		break;
-	default:
+	else if (rate >= 125 * MHz)
+		src_clk = SCLK_SFC_SEL_125M;
+	else if (rate >= 100 * MHz)
+		src_clk = SCLK_SFC_SEL_100M;
+	else if (rate >= 75 * MHz)
+		src_clk = SCLK_SFC_SEL_75M;
+	else if (rate >= 50 * MHz)
+		src_clk = SCLK_SFC_SEL_50M;
+	else if (rate >= OSC_HZ)
+		src_clk = SCLK_SFC_SEL_24M;
+	else
 		return -ENOENT;
-	}
 
 	rk_clrsetreg(&cru->clksel_con[28],
 		     SCLK_SFC_SEL_MASK,