From: Dirk Behme <dirk.behme@de.bosch.com>
Date: Thu, 12 Apr 2012 20:46:14 +0000 (+0000)
Subject: i.MX6: arm2: Add AXI cache and Qos setting
X-Git-Url: http://git.dujemihanovic.xyz/img/sics.gif?a=commitdiff_plain;h=03f3587822839d90b1b118d3cd51c59d8b4d5b32;p=u-boot.git

i.MX6: arm2: Add AXI cache and Qos setting

Do the same AXI cache and Qos settings done already in the
SabreLite imximage.cfg for the ARM2 board, too.

It fixes a display flash issue caused by low priority of
the display IDMA channel.

Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
CC: Jason Chen <b02280@freescale.com>
CC: Jason Liu <r64343@freescale.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <festevam@gmail.com>
Acked-by: Jason Liu <r64343@freescale.com>
---

diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg
index 5f0ee0d190..ceecbf925d 100644
--- a/board/freescale/mx6qarm2/imximage.cfg
+++ b/board/freescale/mx6qarm2/imximage.cfg
@@ -165,3 +165,9 @@ DATA 4 0x020c4074 0x3FF00000
 DATA 4 0x020c4078 0x00FFF300
 DATA 4 0x020c407c 0x0F0000C3
 DATA 4 0x020c4080 0x000003FF
+
+# enable AXI cache for VDOA/VPU/IPU
+DATA 4 0x020e0010 0xF00000FF
+# set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F