#define BOARD_GPP_POL_LOW 0x0
#define BOARD_GPP_POL_MID 0x0
-static struct tlv_data cf_tlv_data;
+static struct tlv_data cf_tlv_data = { 0 };
static void cf_read_tlv_data(void)
{
break;
}
+ switch (cf_tlv_data.ram_channels) {
+ default:
+ case 1:
+ for (uint8_t i = 0; i < 5; i++)
+ ifp->as_bus_params[i].cs_bitmask = 0x1;
+ break;
+ case 2:
+ for (uint8_t i = 0; i < 5; i++)
+ ifp->as_bus_params[i].cs_bitmask = 0x3;
+ break;
+ }
+
/* Return the board topology as defined in the board code */
return &board_topology_map;
}
if (val[4] != SR_TLV_CODE_RAM_SIZE)
return;
- if (tlv_entry->length != 6)
+ if (tlv_entry->length < 6)
return;
td->ram_size = val[5];
+
+ /* extension with additional data field for number of ddr channels */
+ if (tlv_entry->length >= 7) {
+ td->ram_channels = val[6];
+ }
}
static void parse_tlv_data(u8 *eeprom, struct tlvinfo_header *hdr,