]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
armv8: ls1046aqds: add lpuart support
authorShaohui Xie <Shaohui.Xie@nxp.com>
Fri, 28 Oct 2016 06:24:02 +0000 (14:24 +0800)
committerYork Sun <york.sun@nxp.com>
Mon, 21 Nov 2016 17:20:32 +0000 (09:20 -0800)
LPUART0 is used by default, and it's using platform clock.

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
arch/arm/dts/Makefile
arch/arm/dts/fsl-ls1046a-qds-lpuart.dts [new file with mode: 0644]
arch/arm/dts/fsl-ls1046a-qds.dtsi
arch/arm/dts/fsl-ls1046a.dtsi
board/freescale/ls1046aqds/ls1046aqds.c
configs/ls1046aqds_lpuart_defconfig [new file with mode: 0644]
include/configs/ls1046aqds.h

index 36133f59e301fdb3f13d179067bef427b7b1a0fd..26f1e92ee4a7127be7d2d3075cb468e5a71bc90c 100644 (file)
@@ -151,6 +151,7 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
        fsl-ls1043a-qds-lpuart.dtb \
        fsl-ls1043a-rdb.dtb \
        fsl-ls1046a-qds-duart.dtb \
+       fsl-ls1046a-qds-lpuart.dtb \
        fsl-ls1046a-rdb.dtb \
        fsl-ls1012a-qds.dtb \
        fsl-ls1012a-rdb.dtb \
diff --git a/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts b/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts
new file mode 100644 (file)
index 0000000..21243d0
--- /dev/null
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright (C) 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1046a-qds.dtsi"
+
+/ {
+       chosen {
+               stdout-path = &lpuart0;
+       };
+};
index c5122930fe13a65e26bba6a3a0896dcebd49dc94..a49ca08d888eb2f9e1cfe83138adb7f41029e38b 100644 (file)
@@ -75,3 +75,7 @@
 &duart1 {
        status = "okay";
 };
+
+&lpuart0 {
+       status = "okay";
+};
index 87dd9976d154aa6fbad1a4a64f4374d131e55406..359a9d13bf8e6397d462b84a40240204fbfb6271 100644 (file)
                        clocks = <&clockgen 4 0>;
                };
 
+               lpuart0: serial@2950000 {
+                       compatible = "fsl,ls1021a-lpuart";
+                       reg = <0x0 0x2950000 0x0 0x1000>;
+                       interrupts = <0 48 0x4>;
+                       clocks = <&clockgen 4 0>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+
+               lpuart1: serial@2960000 {
+                       compatible = "fsl,ls1021a-lpuart";
+                       reg = <0x0 0x2960000 0x0 0x1000>;
+                       interrupts = <0 49 0x4>;
+                       clocks = <&clockgen 4 1>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+
+               lpuart2: serial@2970000 {
+                       compatible = "fsl,ls1021a-lpuart";
+                       reg = <0x0 0x2970000 0x0 0x1000>;
+                       interrupts = <0 50 0x4>;
+                       clocks = <&clockgen 4 1>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+
+               lpuart3: serial@2980000 {
+                       compatible = "fsl,ls1021a-lpuart";
+                       reg = <0x0 0x2980000 0x0 0x1000>;
+                       interrupts = <0 51 0x4>;
+                       clocks = <&clockgen 4 1>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+
+               lpuart4: serial@2990000 {
+                       compatible = "fsl,ls1021a-lpuart";
+                       reg = <0x0 0x2990000 0x0 0x1000>;
+                       interrupts = <0 52 0x4>;
+                       clocks = <&clockgen 4 1>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+
+               lpuart5: serial@29a0000 {
+                       compatible = "fsl,ls1021a-lpuart";
+                       reg = <0x0 0x29a0000 0x0 0x1000>;
+                       interrupts = <0 53 0x4>;
+                       clocks = <&clockgen 4 1>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+
                qspi: quadspi@1550000 {
                        compatible = "fsl,vf610-qspi";
                        #address-cells = <1>;
index 8c1853850308b6831f83e750e9636c683469c437..552365b9d88854afd9d529e21739a8d828352675 100644 (file)
@@ -120,6 +120,13 @@ unsigned long get_board_ddr_clk(void)
        return 66666666;
 }
 
+#ifdef CONFIG_LPUART
+u32 get_lpuart_clk(void)
+{
+       return gd->bus_clk;
+}
+#endif
+
 int select_i2c_ch_pca9547(u8 ch)
 {
        int ret;
@@ -157,6 +164,9 @@ int board_early_init_f(void)
        struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
        u32 usb_pwrfault;
 #endif
+#ifdef CONFIG_LPUART
+       u8 uart;
+#endif
 
 #ifdef CONFIG_SYS_I2C_EARLY_INIT
        i2c_early_init_f();
@@ -175,6 +185,14 @@ int board_early_init_f(void)
        out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 #endif
 
+#ifdef CONFIG_LPUART
+       /* We use lpuart0 as system console */
+       uart = QIXIS_READ(brdcfg[14]);
+       uart &= ~CFG_UART_MUX_MASK;
+       uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
+       QIXIS_WRITE(brdcfg[14], uart);
+#endif
+
        return 0;
 }
 
diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig
new file mode 100644 (file)
index 0000000..25bb5f9
--- /dev/null
@@ -0,0 +1,30 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1046AQDS=y
+CONFIG_SYS_FSL_DDR4=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-lpuart"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_BOOTDELAY=10
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_FSL_DSPI=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
index c0f5bd3562e72d96450aa7efa627388cc1c68bae..29e0aa5ee1e0941b6767b6ab78d13d5149998982 100644 (file)
@@ -127,6 +127,14 @@ unsigned long get_board_ddr_clk(void);
 #endif
 #endif
 
+/* LPUART */
+#ifdef CONFIG_LPUART
+#define CONFIG_LPUART_32B_REG
+#define CFG_UART_MUX_MASK      0x6
+#define CFG_UART_MUX_SHIFT     1
+#define CFG_LPUART_EN          0x2
+#endif
+
 /* SATA */
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI