board/t2080rdb: reset cs4315 phy

CS4315 PHY doesn't support phy-reset by software, it
needs to reset it by hardware via CPLD control.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/board/freescale/t208xrdb/cpld.h b/board/freescale/t208xrdb/cpld.h
index 3f1533888ddf51acd9a0e3c9e2b40027268fa318..9bd5247563441487d9d54d0de38c7730ca5dfc92 100644 (file)
--- a/board/freescale/t208xrdb/cpld.h
+++ b/board/freescale/t208xrdb/cpld.h
@@ -40,3 +40,6 @@ void cpld_write(unsigned int reg, u8 value);
 #define CPLD_LBMAP_RESET       0xFF
 #define CPLD_LBMAP_SHIFT       0x03
 #define CPLD_BOOT_SEL          0x80
+
+/* RSTCON Register */
+#define CPLD_RSTCON_EDC_RST    0x04

diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c
index ad393dfc5c250ddc71999997596886ab8356443f..0c2c1c565bdd115ad1332cfd43598bf710c19330 100644 (file)
--- a/board/freescale/t208xrdb/t208xrdb.c
+++ b/board/freescale/t208xrdb/t208xrdb.c
@@ -107,6 +107,13 @@ unsigned long get_board_ddr_clk(void)
 
 int misc_init_r(void)
 {
+       u8 reg;
+
+       /* Reset CS4315 PHY */
+       reg = CPLD_READ(reset_ctl);
+       reg |= CPLD_RSTCON_EDC_RST;
+       CPLD_WRITE(reset_ctl, reg);
+
        return 0;
 }