riscv: Do not build reset.c if SYSRESET is on

SYSRESET uclass driver already provides all the reset APIs, hence
exclude our own ad-hoc reset.c implementation.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Sagar Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>

diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index b5e93244e0ecb18f2a49f5b64333ebd2cf138369..6c503ff2b2b7a0dfd85bea8648348499a50982f0 100644 (file)
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -20,7 +20,9 @@ obj-$(CONFIG_SBI) += sbi.o
 obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
 endif
 obj-y  += interrupts.o
+ifeq ($(CONFIG_$(SPL_)SYSRESET),)
 obj-y  += reset.o
+endif
 obj-y   += setjmp.o
 obj-$(CONFIG_$(SPL_)SMP) += smp.o
 obj-$(CONFIG_SPL_BUILD)        += spl.o