clk: microchip: mpfs: convert parent rate acquistion to get_get_rate()

Currently the clock driver for PolarFire SoC takes a very naive approach
to the relationship between clocks. It reads the dt to get an input
clock, assumes that that is fixed frequency, reads the "clock-frequency"
property & uses that to set up both the "cfg" and "periph" clocks.

Simplifying for the sake of incremental fixes, the "correct" parentage for
the clocks currently supported in U-Boot is that the "cfg" clocks should
be children of the fixed frequency clock in the dt. The AHB clock is one
of these "cfg" clocks and is the parent of the "periph" clocks.

Instead of passing the clock rate of the fixed-frequency clock to the
"cfg" and "periph" registration functions and the name of the parents,
pass their actual parents & use clk_get_rate() to determine their parents
rates.

The "periph" clocks are purely gate clocks and should not be reading the
AHB clocks registers to determine their rates, as they can simply report
the output of clk_get_rate() on their parent.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>

diff --git a/drivers/clk/microchip/Makefile b/drivers/clk/microchip/Makefile
index 904b345d75f8a1ef3d72b94094ea0f6546006795..329b2c0c93f3332ece3073264565eabb48c63fcb 100644 (file)
--- a/drivers/clk/microchip/Makefile
+++ b/drivers/clk/microchip/Makefile
@@ -1 +1 @@
-obj-y += mpfs_clk.o mpfs_clk_cfg.o mpfs_clk_periph.o
+obj-y += mpfs_clk.o mpfs_clk_cfg.o mpfs_clk_periph.o mpfs_clk_msspll.o

diff --git a/drivers/clk/microchip/mpfs_clk.c b/drivers/clk/microchip/mpfs_clk.c
index 67828c9bf404deb426b70d7d7b1cf21f103165a6..7ba1218b56e04c7c1dbcb4e533473218d812808c 100644 (file)
--- a/drivers/clk/microchip/mpfs_clk.c
+++ b/drivers/clk/microchip/mpfs_clk.c
@@ -11,34 +11,32 @@
 #include <dm/device.h>
 #include <dm/devres.h>
 #include <dm/uclass.h>
+#include <dt-bindings/clock/microchip-mpfs-clock.h>
 #include <linux/err.h>
 
 #include "mpfs_clk.h"
 
 static int mpfs_clk_probe(struct udevice *dev)
 {
-       int ret;
+       struct clk *parent_clk = dev_get_priv(dev);
+       struct clk clk_ahb = { .id = CLK_AHB };
        void __iomem *base;
-       u32 clk_rate;
-       const char *parent_clk_name;
-       struct clk *clk = dev_get_priv(dev);
+       int ret;
 
        base = dev_read_addr_ptr(dev);
        if (!base)
                return -EINVAL;
 
-       ret = clk_get_by_index(dev, 0, clk);
+       ret = clk_get_by_index(dev, 0, parent_clk);
        if (ret)
                return ret;
 
-       dev_read_u32(clk->dev, "clock-frequency", &clk_rate);
-       parent_clk_name = clk->dev->name;
-
-       ret = mpfs_clk_register_cfgs(base, clk_rate, parent_clk_name);
+       ret = mpfs_clk_register_cfgs(base, parent_clk);
        if (ret)
                return ret;
 
-       ret = mpfs_clk_register_periphs(base, clk_rate, "clk_ahb");
+       clk_request(dev, &clk_ahb);
+       ret = mpfs_clk_register_periphs(base, &clk_ahb);
 
        return ret;
 }

diff --git a/drivers/clk/microchip/mpfs_clk.h b/drivers/clk/microchip/mpfs_clk.h
index 442562a5e7bfbf42bdbb53bfbf96cd8afe1414cf..35cfeac92e8f0b6989bf8ea8fc4923a1f78ed410 100644 (file)
--- a/drivers/clk/microchip/mpfs_clk.h
+++ b/drivers/clk/microchip/mpfs_clk.h
@@ -11,22 +11,18 @@
  * mpfs_clk_register_cfgs() - register configuration clocks
  *
  * @base: base address of the mpfs system register.
- * @clk_rate: the mpfs pll clock rate.
- * @parent_name: a pointer to parent clock name.
+ * @parent: a pointer to parent clock.
  * Return: zero on success, or a negative error code.
  */
-int mpfs_clk_register_cfgs(void __iomem *base, u32 clk_rate,
-                          const char *parent_name);
+int mpfs_clk_register_cfgs(void __iomem *base, struct clk *parent);
 /**
  * mpfs_clk_register_periphs() - register peripheral clocks
  *
  * @base: base address of the mpfs system register.
- * @clk_rate: the mpfs pll clock rate.
- * @parent_name: a pointer to parent clock name.
+ * @parent: a pointer to parent clock.
  * Return: zero on success, or a negative error code.
  */
-int mpfs_clk_register_periphs(void __iomem *base, u32 clk_rate,
-                             const char *parent_name);
+int mpfs_clk_register_periphs(void __iomem *base, struct clk *parent);
 /**
  * divider_get_val() - get the clock divider value
  *

diff --git a/drivers/clk/microchip/mpfs_clk_cfg.c b/drivers/clk/microchip/mpfs_clk_cfg.c
index fefddd141373f9a2bae1c51dffc911d35d333fe6..5739fd66e8dfb7caf9dca36e2950d92829a4764a 100644 (file)
--- a/drivers/clk/microchip/mpfs_clk_cfg.c
+++ b/drivers/clk/microchip/mpfs_clk_cfg.c
@@ -117,8 +117,7 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = {
        CLK_CFG(CLK_AHB, "clk_ahb", 4, 2, mpfs_div_ahb_table, 0),
 };
 
-int mpfs_clk_register_cfgs(void __iomem *base, u32 clk_rate,
-                          const char *parent_name)
+int mpfs_clk_register_cfgs(void __iomem *base, struct clk *parent)
 {
        int ret;
        int i, id, num_clks;
@@ -129,9 +128,9 @@ int mpfs_clk_register_cfgs(void __iomem *base, u32 clk_rate,
        for (i = 0; i < num_clks; i++) {
                hw = &mpfs_cfg_clks[i].hw;
                mpfs_cfg_clks[i].sys_base = base;
-               mpfs_cfg_clks[i].prate = clk_rate;
+               mpfs_cfg_clks[i].prate = clk_get_rate(parent);
                name = mpfs_cfg_clks[i].cfg.name;
-               ret = clk_register(hw, MPFS_CFG_CLOCK, name, parent_name);
+               ret = clk_register(hw, MPFS_CFG_CLOCK, name, parent->dev->name);
                if (ret)
                        ERR_PTR(ret);
                id = mpfs_cfg_clks[i].cfg.id;

diff --git a/drivers/clk/microchip/mpfs_clk_periph.c b/drivers/clk/microchip/mpfs_clk_periph.c
index 61d90eb4a8585bc94f6380f2aa2701a2c6ac0e7f..1488ef503ed039e6c78dd08d59f0362651deac2c 100644 (file)
--- a/drivers/clk/microchip/mpfs_clk_periph.c
+++ b/drivers/clk/microchip/mpfs_clk_periph.c
@@ -99,16 +99,9 @@ static int mpfs_periph_clk_disable(struct clk *hw)
 static ulong mpfs_periph_clk_recalc_rate(struct clk *hw)
 {
        struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
-       void __iomem *base_addr = periph_hw->sys_base;
-       unsigned long rate;
-       u32 val;
 
-       val = readl(base_addr + REG_CLOCK_CONFIG_CR) >> CFG_AHB_SHIFT;
-       val &= clk_div_mask(CFG_WIDTH);
-       rate = periph_hw->prate / (1u << val);
-       hw->rate = rate;
+       return periph_hw->prate;
 
-       return rate;
 }
 
 #define CLK_PERIPH(_id, _name, _shift, _flags) {       \
@@ -150,8 +143,7 @@ static struct mpfs_periph_hw_clock mpfs_periph_clks[] = {
        CLK_PERIPH(CLK_CFM, "clk_periph_cfm", 29, 0),
 };
 
-int mpfs_clk_register_periphs(void __iomem *base, u32 clk_rate,
-                             const char *parent_name)
+int mpfs_clk_register_periphs(void __iomem *base, struct clk *parent)
 {
        int ret;
        int i, id, num_clks;
@@ -162,9 +154,9 @@ int mpfs_clk_register_periphs(void __iomem *base, u32 clk_rate,
        for (i = 0; i < num_clks; i++)  {
                hw = &mpfs_periph_clks[i].hw;
                mpfs_periph_clks[i].sys_base = base;
-               mpfs_periph_clks[i].prate = clk_rate;
+               mpfs_periph_clks[i].prate = clk_get_rate(parent);
                name = mpfs_periph_clks[i].periph.name;
-               ret = clk_register(hw, MPFS_PERIPH_CLOCK, name, parent_name);
+               ret = clk_register(hw, MPFS_PERIPH_CLOCK, name, parent->dev->name);
                if (ret)
                        ERR_PTR(ret);
                id = mpfs_periph_clks[i].periph.id;