arm: K3: Update _start instruction

On K3 family SoCs, once the ROM loads image on R5, M3 resets R5 and
expects to start executing from 0x0. In order to handle this ROM
updates the boot vector of R5 such that first 64 bytes of image load
address are mapped to 0x0.

In this case, it is SPL's responsibility to jump to the proper image
location. So, update the PC with address of reset vector(like how
other exception vectors are handled), instead of branching to reset.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S
index d629cb1dc2d2f40dc02c99ae243dd9482de4eb8d..2ca6e2494a7ad4dac2c2ae4ab4c8d573b6eb3f63 100644 (file)
--- a/arch/arm/lib/vectors.S
+++ b/arch/arm/lib/vectors.S
@@ -19,7 +19,11 @@
  * for the non-boot0 case or by a boot0-header.
  */
         .macro ARM_VECTORS
+#ifdef CONFIG_ARCH_K3
+       ldr     pc, _reset
+#else
        b       reset
+#endif
        ldr     pc, _undefined_instruction
        ldr     pc, _software_interrupt
        ldr     pc, _prefetch_abort
@@ -94,6 +98,7 @@ _start:
  *************************************************************************
  */
 
+       .globl  _reset
        .globl  _undefined_instruction
        .globl  _software_interrupt
        .globl  _prefetch_abort
@@ -102,6 +107,9 @@ _start:
        .globl  _irq
        .globl  _fiq
 
+#ifdef CONFIG_ARCH_K3
+_reset:                        .word reset
+#endif
 _undefined_instruction:        .word undefined_instruction
 _software_interrupt:   .word software_interrupt
 _prefetch_abort:       .word prefetch_abort