x86: Tidy up some duplicate MSR defines

Some MSR registers are defined twice in different parts of the file. Move
them together and remove the duplicates. Also drop some thermal defines
which are not used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c
index 2eb917283bc00b932de1850541170a9c2d86bc7b..9394eab956ba1fca12e1f08ed9aa13b8396c4838 100644 (file)
--- a/arch/x86/cpu/baytrail/cpu.c
+++ b/arch/x86/cpu/baytrail/cpu.c
@@ -68,9 +68,9 @@ static void set_max_freq(void)
        msr_t msr;
 
        /* Enable speed step */
-       msr = msr_read(MSR_IA32_MISC_ENABLES);
-       msr.lo |= (1 << 16);
-       msr_write(MSR_IA32_MISC_ENABLES, msr);
+       msr = msr_read(MSR_IA32_MISC_ENABLE);
+       msr.lo |= MISC_ENABLE_ENHANCED_SPEEDSTEP;
+       msr_write(MSR_IA32_MISC_ENABLE, msr);
 
        /*
         * Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of

diff --git a/arch/x86/cpu/broadwell/cpu_full.c b/arch/x86/cpu/broadwell/cpu_full.c
index 169b5b02a6ac764ff4abba3e44691cdbdb139965..895edeb4bc423edd8cf17759240365d8d4c7938c 100644 (file)
--- a/arch/x86/cpu/broadwell/cpu_full.c
+++ b/arch/x86/cpu/broadwell/cpu_full.c
@@ -470,9 +470,9 @@ static void configure_misc(void)
        msr_t msr;
 
        msr = msr_read(MSR_IA32_MISC_ENABLE);
-       msr.lo |= (1 << 0);       /* Fast String enable */
-       msr.lo |= (1 << 3);       /* TM1/TM2/EMTTM enable */
-       msr.lo |= (1 << 16);      /* Enhanced SpeedStep Enable */
+       msr.lo |= MISC_ENABLE_FAST_STRING;
+       msr.lo |= MISC_ENABLE_TM1;
+       msr.lo |= MISC_ENABLE_ENHANCED_SPEEDSTEP;
        msr_write(MSR_IA32_MISC_ENABLE, msr);
 
        /* Disable thermal interrupts */

diff --git a/arch/x86/cpu/turbo.c b/arch/x86/cpu/turbo.c
index a41d511238dffb8e6d710034fbd59dfac7980bd3..be468d2b2cac5f5b28ce83effb6eacce0e0a46a1 100644 (file)
--- a/arch/x86/cpu/turbo.c
+++ b/arch/x86/cpu/turbo.c
@@ -60,8 +60,8 @@ int turbo_get_state(void)
        cpuid_regs = cpuid(CPUID_LEAF_PM);
        turbo_cap = !!(cpuid_regs.eax & PM_CAP_TURBO_MODE);
 
-       msr = msr_read(MSR_IA32_MISC_ENABLES);
-       turbo_en = !(msr.hi & H_MISC_DISABLE_TURBO);
+       msr = msr_read(MSR_IA32_MISC_ENABLE);
+       turbo_en = !(msr.hi & MISC_DISABLE_TURBO);
 
        if (!turbo_cap && turbo_en) {
                /* Unavailable */
@@ -86,9 +86,9 @@ void turbo_enable(void)
        /* Only possible if turbo is available but hidden */
        if (turbo_get_state() == TURBO_DISABLED) {
                /* Clear Turbo Disable bit in Misc Enables */
-               msr = msr_read(MSR_IA32_MISC_ENABLES);
-               msr.hi &= ~H_MISC_DISABLE_TURBO;
-               msr_write(MSR_IA32_MISC_ENABLES, msr);
+               msr = msr_read(MSR_IA32_MISC_ENABLE);
+               msr.hi &= ~MISC_DISABLE_TURBO;
+               msr_write(MSR_IA32_MISC_ENABLE, msr);
 
                /* Update cached turbo state */
                set_global_turbo_state(TURBO_ENABLED);

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 6cb58708090897b727a9c92a228380b564bdb73f..5bc8b6c22c7eab17ed1c41446bc5e356b8029b6b 100644 (file)
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -92,7 +92,38 @@
 /* This is burst mode BIT 38 in IA32_MISC_ENABLE MSR at offset 1A0h */
 #define BURST_MODE_DISABLE             (1 << 6)
 
-#define MSR_IA32_MISC_ENABLES          0x000001a0
+#define MSR_IA32_MISC_ENABLE           0x000001a0
+
+/* MISC_ENABLE bits: architectural */
+#define MISC_ENABLE_FAST_STRING                BIT_ULL(0)
+#define MISC_ENABLE_TCC                        BIT_ULL(1)
+#define MISC_DISABLE_TURBO             BIT_ULL(6)
+#define MISC_ENABLE_EMON               BIT_ULL(7)
+#define MISC_ENABLE_BTS_UNAVAIL                BIT_ULL(11)
+#define MISC_ENABLE_PEBS_UNAVAIL       BIT_ULL(12)
+#define MISC_ENABLE_ENHANCED_SPEEDSTEP BIT_ULL(16)
+#define MISC_ENABLE_MWAIT              BIT_ULL(18)
+#define MISC_ENABLE_LIMIT_CPUID                BIT_ULL(22)
+#define MISC_ENABLE_XTPR_DISABLE       BIT_ULL(23)
+#define MISC_ENABLE_XD_DISABLE         BIT_ULL(34)
+
+/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
+#define MISC_ENABLE_X87_COMPAT         BIT_ULL(2)
+#define MISC_ENABLE_TM1                        BIT_ULL(3)
+#define MISC_ENABLE_SPLIT_LOCK_DISABLE BIT_ULL(4)
+#define MISC_ENABLE_L3CACHE_DISABLE    BIT_ULL(6)
+#define MISC_ENABLE_SUPPRESS_LOCK      BIT_ULL(8)
+#define MISC_ENABLE_PREFETCH_DISABLE   BIT_ULL(9)
+#define MISC_ENABLE_FERR               BIT_ULL(10)
+#define MISC_ENABLE_FERR_MULTIPLEX     BIT_ULL(10)
+#define MISC_ENABLE_TM2                        BIT_ULL(13)
+#define MISC_ENABLE_ADJ_PREF_DISABLE   BIT_ULL(19)
+#define MISC_ENABLE_SPEEDSTEP_LOCK     BIT_ULL(20)
+#define MISC_ENABLE_L1D_CONTEXT                BIT_ULL(24)
+#define MISC_ENABLE_DCU_PREF_DISABLE   BIT_ULL(37)
+#define MISC_ENABLE_TURBO_DISABLE      BIT_ULL(38)
+#define MISC_ENABLE_IP_PREF_DISABLE    BIT_ULL(39)
+
 #define MSR_TEMPERATURE_TARGET         0x1a2
 #define MSR_PREFETCH_CTL               0x1a4
 #define  PREFETCH_L1_DISABLE           (1 << 0)
@@ -108,6 +139,17 @@
 #define  ENERGY_POLICY_NORMAL          6
 #define  ENERGY_POLICY_POWERSAVE       15
 
+#define MSR_IA32_PACKAGE_THERM_STATUS          0x000001b1
+
+#define PACKAGE_THERM_STATUS_PROCHOT           BIT(0)
+#define PACKAGE_THERM_STATUS_POWER_LIMIT       BIT(10)
+
+#define MSR_IA32_PACKAGE_THERM_INTERRUPT       0x000001b2
+
+#define PACKAGE_THERM_INT_HIGH_ENABLE          BIT(0)
+#define PACKAGE_THERM_INT_LOW_ENABLE           BIT(1)
+#define PACKAGE_THERM_INT_PLN_ENABLE           BIT(24)
+
 #define MSR_LBR_SELECT                 0x000001c8
 #define MSR_LBR_TOS                    0x000001c9
 #define MSR_IA32_PLATFORM_DCA_CAP      0x1f8
@@ -419,68 +461,6 @@
 
 #define MSR_THERM2_CTL_TM_SELECT       (1ULL << 16)
 
-#define MSR_IA32_MISC_ENABLE           0x000001a0
-#define H_MISC_DISABLE_TURBO           (1 << 6)
-
-#define MSR_IA32_TEMPERATURE_TARGET    0x000001a2
-
-#define MSR_IA32_ENERGY_PERF_BIAS      0x000001b0
-#define ENERGY_PERF_BIAS_PERFORMANCE   0
-#define ENERGY_PERF_BIAS_NORMAL                6
-#define ENERGY_PERF_BIAS_POWERSAVE     15
-
-#define MSR_IA32_PACKAGE_THERM_STATUS          0x000001b1
-
-#define PACKAGE_THERM_STATUS_PROCHOT           (1 << 0)
-#define PACKAGE_THERM_STATUS_POWER_LIMIT       (1 << 10)
-
-#define MSR_IA32_PACKAGE_THERM_INTERRUPT       0x000001b2
-
-#define PACKAGE_THERM_INT_HIGH_ENABLE          (1 << 0)
-#define PACKAGE_THERM_INT_LOW_ENABLE           (1 << 1)
-#define PACKAGE_THERM_INT_PLN_ENABLE           (1 << 24)
-
-/* Thermal Thresholds Support */
-#define THERM_INT_THRESHOLD0_ENABLE    (1 << 15)
-#define THERM_SHIFT_THRESHOLD0        8
-#define THERM_MASK_THRESHOLD0          (0x7f << THERM_SHIFT_THRESHOLD0)
-#define THERM_INT_THRESHOLD1_ENABLE    (1 << 23)
-#define THERM_SHIFT_THRESHOLD1        16
-#define THERM_MASK_THRESHOLD1          (0x7f << THERM_SHIFT_THRESHOLD1)
-#define THERM_STATUS_THRESHOLD0        (1 << 6)
-#define THERM_LOG_THRESHOLD0           (1 << 7)
-#define THERM_STATUS_THRESHOLD1        (1 << 8)
-#define THERM_LOG_THRESHOLD1           (1 << 9)
-
-/* MISC_ENABLE bits: architectural */
-#define MSR_IA32_MISC_ENABLE_FAST_STRING       (1ULL << 0)
-#define MSR_IA32_MISC_ENABLE_TCC               (1ULL << 1)
-#define MSR_IA32_MISC_ENABLE_EMON              (1ULL << 7)
-#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL       (1ULL << 11)
-#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL      (1ULL << 12)
-#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP        (1ULL << 16)
-#define MSR_IA32_MISC_ENABLE_MWAIT             (1ULL << 18)
-#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID       (1ULL << 22)
-#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE      (1ULL << 23)
-#define MSR_IA32_MISC_ENABLE_XD_DISABLE                (1ULL << 34)
-
-/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
-#define MSR_IA32_MISC_ENABLE_X87_COMPAT                (1ULL << 2)
-#define MSR_IA32_MISC_ENABLE_TM1               (1ULL << 3)
-#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE        (1ULL << 4)
-#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE   (1ULL << 6)
-#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK     (1ULL << 8)
-#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE  (1ULL << 9)
-#define MSR_IA32_MISC_ENABLE_FERR              (1ULL << 10)
-#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX    (1ULL << 10)
-#define MSR_IA32_MISC_ENABLE_TM2               (1ULL << 13)
-#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE  (1ULL << 19)
-#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK    (1ULL << 20)
-#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT       (1ULL << 24)
-#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE  (1ULL << 37)
-#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE     (1ULL << 38)
-#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE   (1ULL << 39)
-
 #define MSR_IA32_TSC_DEADLINE          0x000006E0
 
 /* P4/Xeon+ specific */