spi: tegra: Use BIT macro

Replace numerical bit shift with BIT macro
in tegra*.c

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tom Warren <twarren@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>

diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c
index a965f80aebb5b5f5e95a27e80395d2651a09b09a..d9edd118a9a9287fd8584a216f91a1140baee908 100644 (file)
--- a/drivers/spi/tegra114_spi.c
+++ b/drivers/spi/tegra114_spi.c
@@ -33,54 +33,54 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* COMMAND1 */
-#define SPI_CMD1_GO                    (1 << 31)
-#define SPI_CMD1_M_S                   (1 << 30)
+#define SPI_CMD1_GO                    BIT(31)
+#define SPI_CMD1_M_S                   BIT(30)
 #define SPI_CMD1_MODE_MASK             0x3
 #define SPI_CMD1_MODE_SHIFT            28
 #define SPI_CMD1_CS_SEL_MASK           0x3
 #define SPI_CMD1_CS_SEL_SHIFT          26
-#define SPI_CMD1_CS_POL_INACTIVE3      (1 << 25)
-#define SPI_CMD1_CS_POL_INACTIVE2      (1 << 24)
-#define SPI_CMD1_CS_POL_INACTIVE1      (1 << 23)
-#define SPI_CMD1_CS_POL_INACTIVE0      (1 << 22)
-#define SPI_CMD1_CS_SW_HW              (1 << 21)
-#define SPI_CMD1_CS_SW_VAL             (1 << 20)
+#define SPI_CMD1_CS_POL_INACTIVE3      BIT(25)
+#define SPI_CMD1_CS_POL_INACTIVE2      BIT(24)
+#define SPI_CMD1_CS_POL_INACTIVE1      BIT(23)
+#define SPI_CMD1_CS_POL_INACTIVE0      BIT(22)
+#define SPI_CMD1_CS_SW_HW              BIT(21)
+#define SPI_CMD1_CS_SW_VAL             BIT(20)
 #define SPI_CMD1_IDLE_SDA_MASK         0x3
 #define SPI_CMD1_IDLE_SDA_SHIFT                18
-#define SPI_CMD1_BIDIR                 (1 << 17)
-#define SPI_CMD1_LSBI_FE               (1 << 16)
-#define SPI_CMD1_LSBY_FE               (1 << 15)
-#define SPI_CMD1_BOTH_EN_BIT           (1 << 14)
-#define SPI_CMD1_BOTH_EN_BYTE          (1 << 13)
-#define SPI_CMD1_RX_EN                 (1 << 12)
-#define SPI_CMD1_TX_EN                 (1 << 11)
-#define SPI_CMD1_PACKED                        (1 << 5)
+#define SPI_CMD1_BIDIR                 BIT(17)
+#define SPI_CMD1_LSBI_FE               BIT(16)
+#define SPI_CMD1_LSBY_FE               BIT(15)
+#define SPI_CMD1_BOTH_EN_BIT           BIT(14)
+#define SPI_CMD1_BOTH_EN_BYTE          BIT(13)
+#define SPI_CMD1_RX_EN                 BIT(12)
+#define SPI_CMD1_TX_EN                 BIT(11)
+#define SPI_CMD1_PACKED                        BIT(5)
 #define SPI_CMD1_BIT_LEN_MASK          0x1F
 #define SPI_CMD1_BIT_LEN_SHIFT         0
 
 /* COMMAND2 */
-#define SPI_CMD2_TX_CLK_TAP_DELAY      (1 << 6)
+#define SPI_CMD2_TX_CLK_TAP_DELAY      BIT(6)
 #define SPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F << 6)
-#define SPI_CMD2_RX_CLK_TAP_DELAY      (1 << 0)
+#define SPI_CMD2_RX_CLK_TAP_DELAY      BIT(0)
 #define SPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F << 0)
 
 /* TRANSFER STATUS */
-#define SPI_XFER_STS_RDY               (1 << 30)
+#define SPI_XFER_STS_RDY               BIT(30)
 
 /* FIFO STATUS */
-#define SPI_FIFO_STS_CS_INACTIVE       (1 << 31)
-#define SPI_FIFO_STS_FRAME_END         (1 << 30)
-#define SPI_FIFO_STS_RX_FIFO_FLUSH     (1 << 15)
-#define SPI_FIFO_STS_TX_FIFO_FLUSH     (1 << 14)
-#define SPI_FIFO_STS_ERR               (1 << 8)
-#define SPI_FIFO_STS_TX_FIFO_OVF       (1 << 7)
-#define SPI_FIFO_STS_TX_FIFO_UNR       (1 << 6)
-#define SPI_FIFO_STS_RX_FIFO_OVF       (1 << 5)
-#define SPI_FIFO_STS_RX_FIFO_UNR       (1 << 4)
-#define SPI_FIFO_STS_TX_FIFO_FULL      (1 << 3)
-#define SPI_FIFO_STS_TX_FIFO_EMPTY     (1 << 2)
-#define SPI_FIFO_STS_RX_FIFO_FULL      (1 << 1)
-#define SPI_FIFO_STS_RX_FIFO_EMPTY     (1 << 0)
+#define SPI_FIFO_STS_CS_INACTIVE       BIT(31)
+#define SPI_FIFO_STS_FRAME_END         BIT(30)
+#define SPI_FIFO_STS_RX_FIFO_FLUSH     BIT(15)
+#define SPI_FIFO_STS_TX_FIFO_FLUSH     BIT(14)
+#define SPI_FIFO_STS_ERR               BIT(8)
+#define SPI_FIFO_STS_TX_FIFO_OVF       BIT(7)
+#define SPI_FIFO_STS_TX_FIFO_UNR       BIT(6)
+#define SPI_FIFO_STS_RX_FIFO_OVF       BIT(5)
+#define SPI_FIFO_STS_RX_FIFO_UNR       BIT(4)
+#define SPI_FIFO_STS_TX_FIFO_FULL      BIT(3)
+#define SPI_FIFO_STS_TX_FIFO_EMPTY     BIT(2)
+#define SPI_FIFO_STS_RX_FIFO_FULL      BIT(1)
+#define SPI_FIFO_STS_RX_FIFO_EMPTY     BIT(0)
 
 #define SPI_TIMEOUT            1000
 #define TEGRA_SPI_MAX_FREQ     52000000

diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c
index afa0848dcb0357c8dd26991d9741c049448e9be1..5dc196b0d10f662a5c5d034ea040dc3571b9df22 100644 (file)
--- a/drivers/spi/tegra20_sflash.c
+++ b/drivers/spi/tegra20_sflash.c
@@ -20,37 +20,37 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define SPI_CMD_GO                     (1 << 30)
+#define SPI_CMD_GO                     BIT(30)
 #define SPI_CMD_ACTIVE_SCLK_SHIFT      26
 #define SPI_CMD_ACTIVE_SCLK_MASK       (3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
-#define SPI_CMD_CK_SDA                 (1 << 21)
+#define SPI_CMD_CK_SDA                 BIT(21)
 #define SPI_CMD_ACTIVE_SDA_SHIFT       18
 #define SPI_CMD_ACTIVE_SDA_MASK                (3 << SPI_CMD_ACTIVE_SDA_SHIFT)
-#define SPI_CMD_CS_POL                 (1 << 16)
-#define SPI_CMD_TXEN                   (1 << 15)
-#define SPI_CMD_RXEN                   (1 << 14)
-#define SPI_CMD_CS_VAL                 (1 << 13)
-#define SPI_CMD_CS_SOFT                        (1 << 12)
-#define SPI_CMD_CS_DELAY               (1 << 9)
-#define SPI_CMD_CS3_EN                 (1 << 8)
-#define SPI_CMD_CS2_EN                 (1 << 7)
-#define SPI_CMD_CS1_EN                 (1 << 6)
-#define SPI_CMD_CS0_EN                 (1 << 5)
-#define SPI_CMD_BIT_LENGTH             (1 << 4)
+#define SPI_CMD_CS_POL                 BIT(16)
+#define SPI_CMD_TXEN                   BIT(15)
+#define SPI_CMD_RXEN                   BIT(14)
+#define SPI_CMD_CS_VAL                 BIT(13)
+#define SPI_CMD_CS_SOFT                        BIT(12)
+#define SPI_CMD_CS_DELAY               BIT(9)
+#define SPI_CMD_CS3_EN                 BIT(8)
+#define SPI_CMD_CS2_EN                 BIT(7)
+#define SPI_CMD_CS1_EN                 BIT(6)
+#define SPI_CMD_CS0_EN                 BIT(5)
+#define SPI_CMD_BIT_LENGTH             BIT(4)
 #define SPI_CMD_BIT_LENGTH_MASK                0x0000001F
 
-#define SPI_STAT_BSY                   (1 << 31)
-#define SPI_STAT_RDY                   (1 << 30)
-#define SPI_STAT_RXF_FLUSH             (1 << 29)
-#define SPI_STAT_TXF_FLUSH             (1 << 28)
-#define SPI_STAT_RXF_UNR               (1 << 27)
-#define SPI_STAT_TXF_OVF               (1 << 26)
-#define SPI_STAT_RXF_EMPTY             (1 << 25)
-#define SPI_STAT_RXF_FULL              (1 << 24)
-#define SPI_STAT_TXF_EMPTY             (1 << 23)
-#define SPI_STAT_TXF_FULL              (1 << 22)
-#define SPI_STAT_SEL_TXRX_N            (1 << 16)
-#define SPI_STAT_CUR_BLKCNT            (1 << 15)
+#define SPI_STAT_BSY                   BIT(31)
+#define SPI_STAT_RDY                   BIT(30)
+#define SPI_STAT_RXF_FLUSH             BIT(29)
+#define SPI_STAT_TXF_FLUSH             BIT(28)
+#define SPI_STAT_RXF_UNR               BIT(27)
+#define SPI_STAT_TXF_OVF               BIT(26)
+#define SPI_STAT_RXF_EMPTY             BIT(25)
+#define SPI_STAT_RXF_FULL              BIT(24)
+#define SPI_STAT_TXF_EMPTY             BIT(23)
+#define SPI_STAT_TXF_FULL              BIT(22)
+#define SPI_STAT_SEL_TXRX_N            BIT(16)
+#define SPI_STAT_CUR_BLKCNT            BIT(15)
 
 #define SPI_TIMEOUT            1000
 #define TEGRA_SPI_MAX_FREQ     52000000

diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c
index 144716fd91f68fad2b2e528b9ac5c9ab20e22ad1..d1abac20a119f32bd90b2d0a4c0a6559021680cd 100644 (file)
--- a/drivers/spi/tegra20_slink.c
+++ b/drivers/spi/tegra20_slink.c
@@ -33,45 +33,45 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* COMMAND */
-#define SLINK_CMD_ENB                  (1 << 31)
-#define SLINK_CMD_GO                   (1 << 30)
-#define SLINK_CMD_M_S                  (1 << 28)
+#define SLINK_CMD_ENB                  BIT(31)
+#define SLINK_CMD_GO                   BIT(30)
+#define SLINK_CMD_M_S                  BIT(28)
 #define SLINK_CMD_IDLE_SCLK_DRIVE_LOW  (0 << 24)
-#define SLINK_CMD_IDLE_SCLK_DRIVE_HIGH (1 << 24)
+#define SLINK_CMD_IDLE_SCLK_DRIVE_HIGH BIT(24)
 #define SLINK_CMD_IDLE_SCLK_PULL_LOW   (2 << 24)
 #define SLINK_CMD_IDLE_SCLK_PULL_HIGH  (3 << 24)
 #define SLINK_CMD_IDLE_SCLK_MASK       (3 << 24)
-#define SLINK_CMD_CK_SDA               (1 << 21)
-#define SLINK_CMD_CS_POL               (1 << 13)
-#define SLINK_CMD_CS_VAL               (1 << 12)
-#define SLINK_CMD_CS_SOFT              (1 << 11)
-#define SLINK_CMD_BIT_LENGTH           (1 << 4)
+#define SLINK_CMD_CK_SDA               BIT(21)
+#define SLINK_CMD_CS_POL               BIT(13)
+#define SLINK_CMD_CS_VAL               BIT(12)
+#define SLINK_CMD_CS_SOFT              BIT(11)
+#define SLINK_CMD_BIT_LENGTH           BIT(4)
 #define SLINK_CMD_BIT_LENGTH_MASK      0x0000001F
 /* COMMAND2 */
-#define SLINK_CMD2_TXEN                        (1 << 30)
-#define SLINK_CMD2_RXEN                        (1 << 31)
-#define SLINK_CMD2_SS_EN               (1 << 18)
+#define SLINK_CMD2_TXEN                        BIT(30)
+#define SLINK_CMD2_RXEN                        BIT(31)
+#define SLINK_CMD2_SS_EN               BIT(18)
 #define SLINK_CMD2_SS_EN_SHIFT         18
 #define SLINK_CMD2_SS_EN_MASK          0x000C0000
-#define SLINK_CMD2_CS_ACTIVE_BETWEEN   (1 << 17)
+#define SLINK_CMD2_CS_ACTIVE_BETWEEN   BIT(17)
 /* STATUS */
-#define SLINK_STAT_BSY                 (1 << 31)
-#define SLINK_STAT_RDY                 (1 << 30)
-#define SLINK_STAT_ERR                 (1 << 29)
-#define SLINK_STAT_RXF_FLUSH           (1 << 27)
-#define SLINK_STAT_TXF_FLUSH           (1 << 26)
-#define SLINK_STAT_RXF_OVF             (1 << 25)
-#define SLINK_STAT_TXF_UNR             (1 << 24)
-#define SLINK_STAT_RXF_EMPTY           (1 << 23)
-#define SLINK_STAT_RXF_FULL            (1 << 22)
-#define SLINK_STAT_TXF_EMPTY           (1 << 21)
-#define SLINK_STAT_TXF_FULL            (1 << 20)
-#define SLINK_STAT_TXF_OVF             (1 << 19)
-#define SLINK_STAT_RXF_UNR             (1 << 18)
-#define SLINK_STAT_CUR_BLKCNT          (1 << 15)
+#define SLINK_STAT_BSY                 BIT(31)
+#define SLINK_STAT_RDY                 BIT(30)
+#define SLINK_STAT_ERR                 BIT(29)
+#define SLINK_STAT_RXF_FLUSH           BIT(27)
+#define SLINK_STAT_TXF_FLUSH           BIT(26)
+#define SLINK_STAT_RXF_OVF             BIT(25)
+#define SLINK_STAT_TXF_UNR             BIT(24)
+#define SLINK_STAT_RXF_EMPTY           BIT(23)
+#define SLINK_STAT_RXF_FULL            BIT(22)
+#define SLINK_STAT_TXF_EMPTY           BIT(21)
+#define SLINK_STAT_TXF_FULL            BIT(20)
+#define SLINK_STAT_TXF_OVF             BIT(19)
+#define SLINK_STAT_RXF_UNR             BIT(18)
+#define SLINK_STAT_CUR_BLKCNT          BIT(15)
 /* STATUS2 */
-#define SLINK_STAT2_RXF_FULL_CNT       (1 << 16)
-#define SLINK_STAT2_TXF_FULL_CNT       (1 << 0)
+#define SLINK_STAT2_RXF_FULL_CNT       BIT(16)
+#define SLINK_STAT2_TXF_FULL_CNT       BIT(0)
 
 #define SPI_TIMEOUT            1000
 #define TEGRA_SPI_MAX_FREQ     52000000