imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c, 24));
clk_dm(IMXRT1050_CLK_SEMC,
imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
- clk_dm(IMXRT1050_CLK_LCDIF,
- imx_clk_gate2("lcdif", "lcdif_podf", base + 0x74, 10));
+ clk_dm(IMXRT1050_CLK_LCDIF_APB,
+ imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28));
+ clk_dm(IMXRT1050_CLK_LCDIF_PIX,
+ imx_clk_gate2("lcdif_pix", "lcdif", base + 0x74, 10));
struct clk *clk, *clk1;
#define IMXRT1050_CLK_USDHC2 43
#define IMXRT1050_CLK_LPUART1 44
#define IMXRT1050_CLK_SEMC 45
-#define IMXRT1050_CLK_LCDIF 46
+#define IMXRT1050_CLK_LCDIF_APB 46
#define IMXRT1050_CLK_PLL1_ARM 47
#define IMXRT1050_CLK_PLL2_SYS 48
#define IMXRT1050_CLK_PLL3_USB_OTG 49
#define IMXRT1050_CLK_PLL5_VIDEO 51
#define IMXRT1050_CLK_PLL6_ENET 52
#define IMXRT1050_CLK_PLL7_USB_HOST 53
-#define IMXRT1050_CLK_END 54
+#define IMXRT1050_CLK_LCDIF_PIX 54
+#define IMXRT1050_CLK_END 55
#endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */