arm: dts: arria10: Move uboot specific properties to u-boot.dtsi

Move Uboot specific properties to *u-boot.dtsi files.
Preparation to sync Arria 10 device tree from Linux.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

diff --git a/arch/arm/dts/socfpga_arria10-u-boot.dtsi b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
new file mode 100644 (file)
index 0000000..c637b10
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier:     GPL-2.0
+/*
+ * Copyright (C) 2014, 2020, Intel Corporation
+ */
+
+/ {
+       chosen {
+               tick-timer = &timer2;
+               u-boot,dm-pre-reloc;
+       };
+
+       memory@0 {
+               u-boot,dm-pre-reloc;
+       };
+
+       soc {
+               u-boot,dm-pre-reloc;
+       };
+};
+
+&clkmgr {
+       u-boot,dm-pre-reloc;
+
+       clocks {
+               u-boot,dm-pre-reloc;
+       };
+};
+
+&cb_intosc_hs_div2_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&cb_intosc_ls_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&f2s_free_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&i2c0 {
+       reset-names = "i2c";
+};
+
+&i2c1 {
+       reset-names = "i2c";
+};
+
+&i2c2 {
+       reset-names = "i2c";
+};
+
+&i2c3 {
+       reset-names = "i2c";
+};
+
+&i2c4 {
+       reset-names = "i2c";
+};
+
+&l4_mp_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&l4_sp_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&l4_sys_free_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&main_periph_ref_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&main_pll {
+       u-boot,dm-pre-reloc;
+};
+
+&main_noc_base_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&noc_free_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&osc1 {
+       u-boot,dm-pre-reloc;
+};
+
+&peri_noc_base_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&periph_pll {
+       u-boot,dm-pre-reloc;
+};
+
+&porta {
+       bank-name = "porta";
+};
+
+&portb {
+       bank-name = "portb";
+};
+
+&portc {
+       bank-name = "portc";
+};
+
+&rst {
+       u-boot,dm-pre-reloc;
+};
+
+&sysmgr {
+       u-boot,dm-pre-reloc;
+};
+
+&timer2 {
+       u-boot,dm-pre-reloc;
+};

diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
index cc529bcd115675a82efb94e2d9d631b08de06693..c8cd5a84b8a848ea96da16bafbdcde1ef55845c8 100644 (file)
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -21,11 +21,6 @@
        #address-cells = <1>;
        #size-cells = <1>;
 
-       chosen {
-               tick-timer = &timer2;
-               u-boot,dm-pre-reloc;
-       };
-
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -60,7 +55,6 @@
                device_type = "soc";
                interrupt-parent = <&intc>;
                ranges;
-               u-boot,dm-pre-reloc;
 
                amba {
                        compatible = "simple-bus";
@@ -99,35 +93,29 @@
                clkmgr: clkmgr@ffd04000 {
                                compatible = "altr,clk-mgr";
                                reg = <0xffd04000 0x1000>;
-                               u-boot,dm-pre-reloc;
 
                                clocks {
                                        #address-cells = <1>;
                                        #size-cells = <0>;
-                                       u-boot,dm-pre-reloc;
 
                                        cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
                                                #clock-cells = <0>;
                                                compatible = "fixed-clock";
-                                               u-boot,dm-pre-reloc;
                                        };
 
                                        cb_intosc_ls_clk: cb_intosc_ls_clk {
                                                #clock-cells = <0>;
                                                compatible = "fixed-clock";
-                                               u-boot,dm-pre-reloc;
                                        };
 
                                        f2s_free_clk: f2s_free_clk {
                                                #clock-cells = <0>;
                                                compatible = "fixed-clock";
-                                               u-boot,dm-pre-reloc;
                                        };
 
                                        osc1: osc1 {
                                                #clock-cells = <0>;
                                                compatible = "fixed-clock";
-                                               u-boot,dm-pre-reloc;
                                        };
 
                                        main_pll: main_pll@40 {
@@ -138,7 +126,6 @@
                                                clocks = <&osc1>, <&cb_intosc_ls_clk>,
                                                         <&f2s_free_clk>;
                                                reg = <0x40>;
-                                               u-boot,dm-pre-reloc;
 
                                                main_mpu_base_clk: main_mpu_base_clk {
                                                        #clock-cells = <0>;
@@ -152,7 +139,6 @@
                                                        compatible = "altr,socfpga-a10-perip-clk";
                                                        clocks = <&main_pll>;
                                                        div-reg = <0x144 0 11>;
-                                                       u-boot,dm-pre-reloc;
                                                };
 
                                                main_emaca_clk: main_emaca_clk@68 {
@@ -228,7 +214,6 @@
                                                clocks = <&osc1>, <&cb_intosc_ls_clk>,
                                                         <&f2s_free_clk>, <&main_periph_ref_clk>;
                                                reg = <0xC0>;
-                                               u-boot,dm-pre-reloc;
 
                                                peri_mpu_base_clk: peri_mpu_base_clk {
                                                        #clock-cells = <0>;
@@ -242,7 +227,6 @@
                                                        compatible = "altr,socfpga-a10-perip-clk";
                                                        clocks = <&periph_pll>;
                                                        div-reg = <0x144 16 11>;
-                                                       u-boot,dm-pre-reloc;
                                                };
 
                                                peri_emaca_clk: peri_emaca_clk@e8 {
@@ -318,7 +302,6 @@
                                                         <&osc1>, <&cb_intosc_hs_div2_clk>,
                                                         <&f2s_free_clk>;
                                                reg = <0x64>;
-                                               u-boot,dm-pre-reloc;
                                        };
 
                                        s2f_user1_free_clk: s2f_user1_free_clk@104 {
@@ -345,7 +328,6 @@
                                                compatible = "altr,socfpga-a10-perip-clk";
                                                clocks = <&noc_free_clk>;
                                                fixed-divider = <4>;
-                                               u-boot,dm-pre-reloc;
                                        };
 
                                        l4_main_clk: l4_main_clk {
@@ -500,7 +482,6 @@
 
                        porta: gpio-controller@0 {
                                compatible = "snps,dw-apb-gpio-port";
-                               bank-name = "porta";
                                gpio-controller;
                                #gpio-cells = <2>;
                                snps,nr-gpios = <29>;
@@ -520,7 +501,6 @@
 
                        portb: gpio-controller@0 {
                                compatible = "snps,dw-apb-gpio-port";
-                               bank-name = "portb";
                                gpio-controller;
                                #gpio-cells = <2>;
                                snps,nr-gpios = <29>;
@@ -540,7 +520,6 @@
 
                        portc: gpio-controller@0 {
                                compatible = "snps,dw-apb-gpio-port";
-                               bank-name = "portc";
                                gpio-controller;
                                #gpio-cells = <2>;
                                snps,nr-gpios = <27>;
@@ -568,7 +547,6 @@
                        interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&l4_sp_clk>;
                        resets = <&rst I2C0_RESET>;
-                       reset-names = "i2c";
                        status = "disabled";
                };
 
@@ -580,7 +558,6 @@
                        interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&l4_sp_clk>;
                        resets = <&rst I2C1_RESET>;
-                       reset-names = "i2c";
                        status = "disabled";
                };
 
@@ -592,7 +569,6 @@
                        interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&l4_sp_clk>;
                        resets = <&rst I2C2_RESET>;
-                       reset-names = "i2c";
                        status = "disabled";
                };
 
@@ -604,7 +580,6 @@
                        interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&l4_sp_clk>;
                        resets = <&rst I2C3_RESET>;
-                       reset-names = "i2c";
                        status = "disabled";
                };
 
@@ -616,7 +591,6 @@
                        interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&l4_sp_clk>;
                        resets = <&rst I2C4_RESET>;
-                       reset-names = "i2c";
                        status = "disabled";
                };
 
@@ -767,7 +741,6 @@
                        compatible = "altr,rst-mgr";
                        reg = <0xffd05000 0x100>;
                        altr,modrst-offset = <0x20>;
-                       u-boot,dm-pre-reloc;
                };
 
                scu: snoop-control-unit@ffffc000 {
@@ -811,7 +784,6 @@
                        reg = <0xffd00000 0x100>;
                        clocks = <&l4_sys_free_clk>;
                        clock-names = "timer";
-                       u-boot,dm-pre-reloc;
                };
 
                timer3: timer3@ffd00100 {

diff --git a/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi
new file mode 100644 (file)
index 0000000..58cd497
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015, 2020 Intel. All rights reserved.
+ */
+
+#include "socfpga_arria10-u-boot.dtsi"
+
+/ {
+       aliases {
+               bootargs = "console=ttyS0,115200";
+               i2c0 = &i2c1;
+       };
+};
+
+&uart1 {
+       u-boot,dm-pre-reloc;
+};

diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi
index ef10708ee867a811afc8d371a27ea3cdb7b922f9..e704243c14c1ee45344942ee3cea26b2c6b41b3d 100644 (file)
--- a/arch/arm/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi
@@ -24,7 +24,6 @@
        aliases {
                ethernet0 = &gmac0;
                serial0 = &uart1;
-               i2c0 = &i2c1;
        };
 
        chosen {
@@ -36,7 +35,6 @@
                name = "memory";
                device_type = "memory";
                reg = <0x0 0x40000000>; /* 1GB */
-               u-boot,dm-pre-reloc;
        };
 
        a10leds {
@@ -63,9 +61,6 @@
                };
        };
 
-       soc {
-               u-boot,dm-pre-reloc;
-       };
 };
 
 &gmac0 {
@@ -155,7 +150,6 @@
 };
 
 &uart1 {
-       u-boot,dm-pre-reloc;
        status = "okay";
 };
 
@@ -167,24 +161,3 @@
 &watchdog1 {
        status = "okay";
 };
-
-/* Clock available early */
-&main_periph_ref_clk {
-       u-boot,dm-pre-reloc;
-};
-
-&l4_mp_clk {
-       u-boot,dm-pre-reloc;
-};
-
-&l4_sp_clk {
-       u-boot,dm-pre-reloc;
-};
-
-&clkmgr {
-       u-boot,dm-pre-reloc;
-};
-
-&sysmgr {
-       u-boot,dm-pre-reloc;
-};

diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi
new file mode 100644 (file)
index 0000000..c229e82
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2014-2015, 2020 Intel. All rights reserved.
+ */
+
+#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
+#include "socfpga_arria10_handoff_u-boot.dtsi"
+#include "socfpga_arria10_socdk-u-boot.dtsi"
+
+/ {
+       chosen {
+               firmware-loader = <&fs_loader0>;
+       };
+
+       fs_loader0: fs-loader {
+               u-boot,dm-pre-reloc;
+               compatible = "u-boot,fs-loader";
+               phandlepart = <&mmc 1>;
+       };
+};
+
+&fpga_mgr {
+       u-boot,dm-pre-reloc;
+       altr,bitstream = "fit_spl_fpga.itb";
+};
+
+&mmc {
+       u-boot,dm-pre-reloc;
+};
+
+/* Clock available early */
+&main_sdmmc_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&peri_sdmmc_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&sdmmc_free_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&sdmmc_clk {
+       u-boot,dm-pre-reloc;
+};

diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
index d6b6c2ddc0914409aabd2e85ce198b6741a049c7..040a164ba148101594a83f0f61d3ac926f1783c1 100644 (file)
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
@@ -17,28 +17,8 @@
 
 /dts-v1/;
 #include "socfpga_arria10_socdk.dtsi"
-#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
-#include "socfpga_arria10_handoff_u-boot.dtsi"
-
-/ {
-       chosen {
-               firmware-loader = <&fs_loader0>;
-       };
-
-       fs_loader0: fs-loader {
-               u-boot,dm-pre-reloc;
-               compatible = "u-boot,fs-loader";
-               phandlepart = <&mmc 1>;
-       };
-};
-
-&fpga_mgr {
-       u-boot,dm-pre-reloc;
-       altr,bitstream = "fit_spl_fpga.itb";
-};
 
 &mmc {
-       u-boot,dm-pre-reloc;
        status = "okay";
        num-slots = <1>;
        cap-sd-highspeed;
@@ -57,20 +37,3 @@
                             <48 IRQ_TYPE_LEVEL_HIGH>;
        };
 };
-
-/* Clock available early */
-&main_sdmmc_clk {
-       u-boot,dm-pre-reloc;
-};
-
-&peri_sdmmc_clk {
-       u-boot,dm-pre-reloc;
-};
-
-&sdmmc_free_clk {
-       u-boot,dm-pre-reloc;
-};
-
-&sdmmc_clk {
-       u-boot,dm-pre-reloc;
-};