arm/errata: Update required bits for A57 cores erratas

This patch updates the setting of required bits for A57 cores erratas
- 828024 and 826974

Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Dai Haruki <dai.haruki at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index e5f2766a4a562fcf005ba45ee9f2081d6a63f2fe..e70bed462a59f9c4d4f1583242f88d99aadb76a9 100644 (file)
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -115,18 +115,18 @@ apply_a57_core_errata:
 #ifdef CONFIG_ARM_ERRATA_828024
        mrs     x0, S3_1_c15_c2_0       /* cpuactlr_el1 */
        /* Disable non-allocate hint of w-b-n-a memory type */
-       mov     x0, #0x1 << 49
+       orr     x0, x0, #1 << 49
        /* Disable write streaming no L1-allocate threshold */
-       mov     x0, #0x3 << 25
+       orr     x0, x0, #3 << 25
        /* Disable write streaming no-allocate threshold */
-       mov     x0, #0x3 << 27
+       orr     x0, x0, #3 << 27
        msr     S3_1_c15_c2_0, x0       /* cpuactlr_el1 */
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_826974
        mrs     x0, S3_1_c15_c2_0       /* cpuactlr_el1 */
        /* Disable speculative load execution ahead of a DMB */
-       mov     x0, #0x1 << 59
+       orr     x0, x0, #1 << 59
        msr     S3_1_c15_c2_0, x0       /* cpuactlr_el1 */
 #endif