riscv: dts: sophgo: add basic device tree for Milk-V Duo board

Import device tree from Linux kernel to add basic support for CPU, PLIC,
UART and Timer. The name cv1800b in the filename represent the chip used
on Milk-V Duo board.

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index b05bb5607f067a51d74a23ed66b752703974a361..17cda483e128996bb944f5a2b9b7676d32e45ae5 100644 (file)
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -2,6 +2,7 @@
 
 dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb
 dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb
+dtb-$(CONFIG_TARGET_MILKV_DUO) += cv1800b-milkv-duo.dtb
 dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
 dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb

diff --git a/arch/riscv/dts/cv1800b-milkv-duo.dts b/arch/riscv/dts/cv1800b-milkv-duo.dts
new file mode 100644 (file)
index 0000000..3af9e34
--- /dev/null
+++ b/arch/riscv/dts/cv1800b-milkv-duo.dts
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ */
+
+/dts-v1/;
+
+#include "cv1800b.dtsi"
+
+/ {
+       model = "Milk-V Duo";
+       compatible = "milkv,duo", "sophgo,cv1800b";
+
+       aliases {
+               serial0 = &uart0;
+               serial1 = &uart1;
+               serial2 = &uart2;
+               serial3 = &uart3;
+               serial4 = &uart4;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory@80000000 {
+               device_type = "memory";
+               reg = <0x80000000 0x3f40000>;
+       };
+};
+
+&osc {
+       clock-frequency = <25000000>;
+};
+
+&uart0 {
+       status = "okay";
+};

diff --git a/arch/riscv/dts/cv1800b.dtsi b/arch/riscv/dts/cv1800b.dtsi
new file mode 100644 (file)
index 0000000..165e9e3
--- /dev/null
+++ b/arch/riscv/dts/cv1800b.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ */
+
+#include "cv18xx.dtsi"
+
+/ {
+       compatible = "sophgo,cv1800b";
+};
+
+&plic {
+       compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
+};
+
+&clint {
+       compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
+};

diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi
new file mode 100644 (file)
index 0000000..2d6f4a4
--- /dev/null
+++ b/arch/riscv/dts/cv18xx.dtsi
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       cpus: cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               timebase-frequency = <25000000>;
+
+               cpu0: cpu@0 {
+                       compatible = "thead,c906", "riscv";
+                       device_type = "cpu";
+                       reg = <0>;
+                       d-cache-block-size = <64>;
+                       d-cache-sets = <512>;
+                       d-cache-size = <65536>;
+                       i-cache-block-size = <64>;
+                       i-cache-sets = <128>;
+                       i-cache-size = <32768>;
+                       mmu-type = "riscv,sv39";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";
+
+                       cpu0_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+       };
+
+       osc: oscillator {
+               compatible = "fixed-clock";
+               clock-output-names = "osc_25m";
+               #clock-cells = <0>;
+       };
+
+       soc {
+               compatible = "simple-bus";
+               interrupt-parent = <&plic>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               dma-noncoherent;
+               ranges;
+
+               gpio0: gpio@3020000 {
+                       compatible = "snps,dw-apb-gpio";
+                       reg = <0x3020000 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       porta: gpio-controller@0 {
+                               compatible = "snps,dw-apb-gpio-port";
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               ngpios = <32>;
+                               reg = <0>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+               };
+
+               gpio1: gpio@3021000 {
+                       compatible = "snps,dw-apb-gpio";
+                       reg = <0x3021000 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       portb: gpio-controller@0 {
+                               compatible = "snps,dw-apb-gpio-port";
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               ngpios = <32>;
+                               reg = <0>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+               };
+
+               gpio2: gpio@3022000 {
+                       compatible = "snps,dw-apb-gpio";
+                       reg = <0x3022000 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       portc: gpio-controller@0 {
+                               compatible = "snps,dw-apb-gpio-port";
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               ngpios = <32>;
+                               reg = <0>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+               };
+
+               gpio3: gpio@3023000 {
+                       compatible = "snps,dw-apb-gpio";
+                       reg = <0x3023000 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       portd: gpio-controller@0 {
+                               compatible = "snps,dw-apb-gpio-port";
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               ngpios = <32>;
+                               reg = <0>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+               };
+
+               uart0: serial@4140000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x04140000 0x100>;
+                       interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&osc>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       status = "disabled";
+               };
+
+               uart1: serial@4150000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x04150000 0x100>;
+                       interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&osc>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       status = "disabled";
+               };
+
+               uart2: serial@4160000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x04160000 0x100>;
+                       interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&osc>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       status = "disabled";
+               };
+
+               uart3: serial@4170000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x04170000 0x100>;
+                       interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&osc>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       status = "disabled";
+               };
+
+               uart4: serial@41c0000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0x041c0000 0x100>;
+                       interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&osc>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       status = "disabled";
+               };
+
+               plic: interrupt-controller@70000000 {
+                       reg = <0x70000000 0x4000000>;
+                       interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
+                       interrupt-controller;
+                       #address-cells = <0>;
+                       #interrupt-cells = <2>;
+                       riscv,ndev = <101>;
+               };
+
+               clint: timer@74000000 {
+                       reg = <0x74000000 0x10000>;
+                       interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
+               };
+       };
+};