imx8mq: fix SSCG_PLL_REFCLK_SEL_x

Fix SSCG_PLL_REFCLK_SEL_x, the offset starts from 0, not 16

Reported-by: Coverity 3448860
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>

diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
index 7109d334fa8b963a1c3b6c8b534c26c5d47651d9..340a61e55bd19195b9454770222fd56e15500b51 100644 (file)
--- a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
+++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
@@ -358,10 +358,10 @@ enum clk_src_index {
 #define SSCG_PLL_LOCK_SEL_MASK         BIT(3)
 #define SSCG_PLL_COUNTCLK_SEL_MASK     BIT(2)
 #define SSCG_PLL_REFCLK_SEL_MASK       0x3
-#define SSCG_PLL_REFCLK_SEL_OSC_25M    (0 << 16)
-#define SSCG_PLL_REFCLK_SEL_OSC_27M    BIT(16)
-#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
-#define SSCG_PLL_REFCLK_SEL_CLK_PN     (3 << 16)
+#define SSCG_PLL_REFCLK_SEL_OSC_25M    (0)
+#define SSCG_PLL_REFCLK_SEL_OSC_27M    (1)
+#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2)
+#define SSCG_PLL_REFCLK_SEL_CLK_PN     (3)
 
 #define SSCG_PLL_SSDS_MASK             BIT(8)
 #define SSCG_PLL_SSMD_MASK             (0x7 << 5)