COMPAT_ALTERA_SOCFPGA_F2SDR0, /* SoCFPGA fpga2SDRAM0 bridge */
COMPAT_ALTERA_SOCFPGA_F2SDR1, /* SoCFPGA fpga2SDRAM1 bridge */
COMPAT_ALTERA_SOCFPGA_F2SDR2, /* SoCFPGA fpga2SDRAM2 bridge */
+ COMPAT_ALTERA_SOCFPGA_FPGA0, /* SOCFPGA FPGA manager */
+ COMPAT_ALTERA_SOCFPGA_NOC, /* SOCFPGA Arria 10 NOC */
COMPAT_COUNT,
};
COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"),
COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"),
COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
+ COMPAT(ALTERA_SOCFPGA_FPGA0, "altr,socfpga-a10-fpga-mgr"),
+ COMPAT(ALTERA_SOCFPGA_NOC, "altr,socfpga-a10-noc"),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)