serial: zynq: Write chars till output fifo is full

Change logic and put char to fifo till there is a space in output fifo.
Origin logic was that output fifo needs to be empty. It means only one
char was in output queue.
Also remove unused ZYNQ_UART_SR_TXEMPTY macro.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
index 7a6f822c26ac0aa9b22031bd7fd4bb8567586978..4ae24939ab23671921ee50777b6580d8e318248a 100644 (file)
--- a/drivers/serial/serial_zynq.c
+++ b/drivers/serial/serial_zynq.c
@@ -15,8 +15,8 @@
 #include <linux/compiler.h>
 #include <serial.h>
 
-#define ZYNQ_UART_SR_TXEMPTY   BIT(3) /* TX FIFO empty */
 #define ZYNQ_UART_SR_TXACTIVE  BIT(11) /* TX active */
+#define ZYNQ_UART_SR_TXFULL    BIT(4) /* TX FIFO full */
 #define ZYNQ_UART_SR_RXEMPTY   BIT(1) /* RX FIFO empty */
 
 #define ZYNQ_UART_CR_TX_EN     BIT(4) /* TX enabled */
@@ -93,7 +93,7 @@ static void _uart_zynq_serial_init(struct uart_zynq *regs)
 
 static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
 {
-       if (!(readl(&regs->channel_sts) & ZYNQ_UART_SR_TXEMPTY))
+       if (readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL)
                return -EAGAIN;
 
        writel(c, &regs->tx_rx_fifo);