mtd: spi-nor-ids: add gigadevice part #

adding gigadevice part numbers

Signed-off-by: Victor Lim <vlim@gigadevice.com>
Link: https://lore.kernel.org/r/20230109234946.14540-2-vlim@gigadevice.com
Signed-off-by: Michal Simek <michal.simek@amd.com>

diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 5f8f3ec955d9149dc5ac900c8c2a35248a6bd6cc..f97e10da876e8c91930f24ce581a729c11b98ac8 100644 (file)
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -118,6 +118,36 @@ const struct flash_info spi_nor_ids[] = {
                        SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
                        SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
        },
+       /* adding these 3V QSPI flash parts */
+       {INFO("gd25b256", 0xc84019, 0, 64 * 1024, 512,  SECT_4K |
+       SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)  },
+       {INFO("gd25b512", 0xc8471A, 0, 64 * 1024, 1024, SECT_4K |
+       SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+       {INFO("gd55b01g", 0xc8471B, 0, 64 * 1024, 2048, SECT_4K |
+       SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+       {INFO("gd55b02g", 0xc8471C, 0, 64 * 1024, 4096, SECT_4K |
+       SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+       {INFO("gd25f64", 0xc84317, 0, 64 * 1024, 128,   SECT_4K |
+       SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
+       {INFO("gd25f128", 0xc84318, 0, 64 * 1024, 256,  SECT_4K |
+       SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
+       {INFO("gd25f256", 0xc84319, 0, 64 * 1024, 512,  SECT_4K |
+       SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+       {INFO("gd55f512", 0xc8431A, 0, 64 * 1024, 1024, SECT_4K |
+       SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+       {INFO("gd25t512", 0xc8461A, 0, 64 * 1024, 1024, SECT_4K |
+       SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+       {INFO("gd55t01g", 0xc8461B, 0, 64 * 1024, 2048, SECT_4K |
+       SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+       {INFO("gd55t02g",       0xc8461C, 0, 64 * 1024, 4096,   SECT_4K |
+       SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+       /* adding these 3V OSPI flash parts */
+       {INFO("gd25x512", 0xc8481A, 0, 64 * 1024, 1024, SECT_4K |
+       SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
+       {INFO("gd55x01g", 0xc8481B, 0, 64 * 1024, 2048, SECT_4K |
+       SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
+       {INFO("gd55x02g", 0xc8481C, 0, 64 * 1024, 4096, SECT_4K |
+       SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
        {
                INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
                        SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
@@ -128,10 +158,48 @@ const struct flash_info spi_nor_ids[] = {
                        SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
                        SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
        },
+       /* adding these 1.8V QSPI flash parts */
+       {INFO("gd25lb256", 0xc86719, 0, 64 * 1024, 512, SECT_4K |
+       SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+       {INFO("gd25lb512", 0xc8671A, 0, 64 * 1024, 1024,        SECT_4K |
+       SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+       {INFO("gd55lb01g", 0xc8671B, 0, 64 * 1024, 2048,        SECT_4K |
+       SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+       {INFO("gd55lb02g", 0xc8671C, 0, 64 * 1024, 4096,        SECT_4K |
+       SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+       {INFO("gd25lf80", 0xc86314, 0, 64 * 1024, 16,   SECT_4K |
+       SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
+       {INFO("gd25lf16", 0xc86315, 0, 64 * 1024, 32,   SECT_4K |
+       SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
+       {INFO("gd25lf32", 0xc86316, 0, 64 * 1024, 64,   SECT_4K |
+       SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)       },
+       {INFO("gd25lf64", 0xc86317, 0, 64 * 1024, 128,  SECT_4K |
+       SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)       },
+       {INFO("gd25lf128", 0xc86318, 0, 64 * 1024, 256, SECT_4K |
+       SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)       },
+       {INFO("gd25lf255", 0xc86319, 0, 64 * 1024, 512, SECT_4K |
+       SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+       {INFO("gd25lf511", 0xc8631A, 0, 64 * 1024, 1024,        SECT_4K |
+       SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+       {INFO("gd25lt256", 0xc86619, 0, 64 * 1024, 512, SECT_4K |
+       SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+       {INFO("gd25lt512", 0xc8661A, 0, 64 * 1024, 1024,        SECT_4K |
+       SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+       {INFO("gd55lt01g", 0xc8661B, 0, 64 * 1024, 2048,        SECT_4K |
+       SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+       {INFO("gd55lt02g", 0xc8661C, 0, 64 * 1024, 4096,        SECT_4K |
+       SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
        {
                INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
                     SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
        },
+       /* adding these 1.8V OSPI flash parts */
+       {INFO("gd25lx512", 0xc8681A, 0, 64 * 1024, 1024,        SECT_4K |
+       SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
+       {INFO("gd55lx01g", 0xc8681B, 0, 64 * 1024, 2048,        SECT_4K |
+       SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
+       {INFO("gd55lx02g", 0xc8681C, 0, 64 * 1024, 4096,        SECT_4K |
+       SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
 #endif
 #ifdef CONFIG_SPI_FLASH_ISSI           /* ISSI */
        /* ISSI */