mpc83xx: remove redundant MPC83xx_RESET #define

This macro is only used (tested for existence) in mpc83xx.c, which
unconditionally includes mpc83xx.h where it is unconditionally
defined. Removing it makes the remaining code easier to read.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>

diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index cefbcf6e817ac9d0b1533a95a420afbc704e238f..49c75a0e5004a2d0a220a57fe10bd1919bd416c6 100644 (file)
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -127,16 +127,10 @@ int checkcpu(void)
 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 {
        ulong msr;
-#ifndef MPC83xx_RESET
-       ulong addr;
-#endif
-
        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 
        puts("Resetting the board.\n");
 
-#ifdef MPC83xx_RESET
-
        /* Interrupts and MMU off */
        msr = mfmsr();
        msr &= ~(MSR_EE | MSR_IR | MSR_DR);
@@ -156,24 +150,6 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
        /* perform reset, only one bit */
        immap->reset.rcr = RCR_SWHR;
 
-#else  /* ! MPC83xx_RESET */
-
-       immap->reset.rmr = RMR_CSRE;    /* Checkstop Reset enable */
-
-       /* Interrupts and MMU off */
-       msr = mfmsr();
-       msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
-       mtmsr(msr);
-
-       /*
-        * Trying to execute the next instruction at a non-existing address
-        * should cause a machine check, resulting in reset
-        */
-       addr = CONFIG_SYS_RESET_ADDRESS;
-
-       ((void (*)(void)) addr) ();
-#endif /* MPC83xx_RESET */
-
        return 1;
 }
 #endif

diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index c2a185321abf0146c25f9bdd73eb0f6acbc7eaea..ea67868ea012ae29da036330186b7400f7f44180 100644 (file)
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -12,11 +12,6 @@
 #include <asm/e300.h>
 #endif
 
-/*
- * MPC83xx cpu provide RCR register to do reset thing specially
- */
-#define MPC83xx_RESET
-
 /*
  * System reset offset (PowerPC standard)
  */