arm: zynq: Fix indentation for zynq-cse targets

Trivial DT style fixes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynq-cse-nand.dts b/arch/arm/dts/zynq-cse-nand.dts
index 9b1dd19a85df4e96b4f1961050f23b8e3317dd7d..1e16d7fab97d178b6dd03ca7e6d383c8c10ea506 100644 (file)
--- a/arch/arm/dts/zynq-cse-nand.dts
+++ b/arch/arm/dts/zynq-cse-nand.dts
@@ -38,7 +38,7 @@
                #size-cells = <1>;
                ranges;
 
-                       slcr: slcr@f8000000 {
+               slcr: slcr@f8000000 {
                        u-boot,dm-pre-reloc;
                        #address-cells = <1>;
                        #size-cells = <1>;
@@ -72,7 +72,6 @@
                        };
                };
        };
-
 };
 
 &dcc {

diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts
index edc8f59f6cea904f9d1529146f76c1289870c7ac..9710abadcf0246d9b83872aef698fb794cc76f17 100644 (file)
--- a/arch/arm/dts/zynq-cse-nor.dts
+++ b/arch/arm/dts/zynq-cse-nor.dts
@@ -79,7 +79,6 @@
                        };
                };
        };
-
 };
 
 &dcc {