imx8ulp: clock: Handle the DDRLOCKED when setting DDR clock

The DDRLOCKED bit in CGC2 DDRCLK will auto lock up and down by HW
according to DDR DIV updating or DDR CLK halt status change. So DDR
PCC disable/enable will trigger the lock up/down flow. We
need wait until unlock to ensure clock is ready.

And before configuring the DDRCLK DIV, we need polling the DDRLOCKED
until it is unlocked. Otherwise writing ti DIV bits will not set.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/include/asm/arch-imx8ulp/cgc.h b/arch/arm/include/asm/arch-imx8ulp/cgc.h
index e15ef1d6c15624051b5bb93b45eb1d9efca84f83..ad3edc85adb738db20ea9cf7f74ed208e6d52609 100644 (file)
--- a/arch/arm/include/asm/arch-imx8ulp/cgc.h
+++ b/arch/arm/include/asm/arch-imx8ulp/cgc.h
@@ -152,6 +152,7 @@ void cgc1_soscdiv_init(void);
 void cgc1_init_core_clk(void);
 void cgc2_pll4_init(void);
 void cgc2_ddrclk_config(u32 src, u32 div);
+void cgc2_ddrclk_wait_unlock(void);
 u32 cgc1_sosc_div(enum cgc_clk clk);
 void cgc1_enet_stamp_sel(u32 clk_src);
 void cgc2_pll4_pfd_config(enum cgc_clk pllpfd, u32 pfd);

diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c
index fc84f3f293808dbcc57377e35e284e02f2fd1f16..38bcbb91e6e8abdc76098b300b48ff1d5cff0e88 100644 (file)
--- a/arch/arm/mach-imx/imx8ulp/cgc.c
+++ b/arch/arm/mach-imx/imx8ulp/cgc.c
@@ -269,12 +269,23 @@ void cgc2_pll4_pfddiv_config(enum cgc_clk pllpfddiv, u32 div)
 
 void cgc2_ddrclk_config(u32 src, u32 div)
 {
+       /* If reg lock is set, wait until unlock by HW */
+       /* This lock is triggered by div updating and ddrclk halt status change, */
+       while ((readl(&cgc2_regs->ddrclk) & BIT(31)))
+               ;
+
        writel((src << 28) | (div << 21), &cgc2_regs->ddrclk);
        /* wait for DDRCLK switching done */
        while (!(readl(&cgc2_regs->ddrclk) & BIT(27)))
                ;
 }
 
+void cgc2_ddrclk_wait_unlock(void)
+{
+       while ((readl(&cgc2_regs->ddrclk) & BIT(31)))
+               ;
+}
+
 void cgc2_lpav_init(enum cgc_clk clk)
 {
        u32 i, scs, reg;

diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c
index 961702310cd7daba4a07f2a005333eae723faf14..91580b2c29ccdce90c71cc2ce77b6b63d6a2ce55 100644 (file)
--- a/arch/arm/mach-imx/imx8ulp/clock.c
+++ b/arch/arm/mach-imx/imx8ulp/clock.c
@@ -107,6 +107,9 @@ void init_clk_ddr(void)
        /* enable ddr pcc */
        writel(0xd0000000, PCC5_LPDDR4_ADDR);
 
+       /* Wait until ddrclk reg lock bit is cleared, so that the div update is finished */
+       cgc2_ddrclk_wait_unlock();
+
        /* for debug */
        /* setclkout_ddr(); */
 }
@@ -144,6 +147,9 @@ int set_ddr_clk(u32 phy_freq_mhz)
                return -EINVAL;
        }
 
+       /* Wait until ddrclk reg lock bit is cleared, so that the div update is finished */
+       cgc2_ddrclk_wait_unlock();
+
        return 0;
 }