imx: imx8mp: add basic clock

i.MX8MP has similar architecture as i.MX8MN, but it has different
clk root and index, so add that to make i.MX8MP could use
the non-dm clock driver.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h
index c910b614ac3f93011f3c37cd0a3d90477971e661..87cc4d3b2b7174bff816e44128db0b0028e9f7b4 100644 (file)
--- a/arch/arm/include/asm/arch-imx8m/clock.h
+++ b/arch/arm/include/asm/arch-imx8m/clock.h
@@ -9,7 +9,8 @@
 
 #ifdef CONFIG_IMX8MQ
 #include <asm/arch/clock_imx8mq.h>
-#elif defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
+#elif defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) || \
+       defined(CONFIG_IMX8MP)
 #include <asm/arch/clock_imx8mm.h>
 #else
 #error "Error no clock.h"

diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
index 76c73edc90fd2afdbbc36072b444f7e8cc7ab786..debed6bac7c08b7ee4f7596b5fec2e743ad3d7fb 100644 (file)
--- a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
+++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
@@ -52,7 +52,109 @@ enum pll_clocks {
        ANATOP_DRAM_PLL,
 };
 
-#ifdef CONFIG_IMX8MN
+#ifdef CONFIG_IMX8MP
+enum clk_root_index {
+       ARM_A53_CLK_ROOT                = 0,
+       ARM_M7_CLK_ROOT                 = 1,
+       ML_CLK_ROOT                     = 2,
+       GPU3D_CORE_CLK_ROOT             = 3,
+       GPU3D_SHADER_CLK_ROOT           = 4,
+       GPU2D_CLK_ROOT                  = 5,
+       AUDIO_AXI_CLK_ROOT              = 6,
+       HSIO_AXI_CLK_ROOT               = 7,
+       MEDIA_ISP_CLK_ROOT              = 8,
+       MAIN_AXI_CLK_ROOT               = 16,
+       ENET_AXI_CLK_ROOT               = 17,
+       NAND_USDHC_BUS_CLK_ROOT         = 18,
+       VPU_BUS_CLK_ROOT                = 19,
+       MEDIA_AXI_CLK_ROOT              = 20,
+       MEDIA_APB_CLK_ROOT              = 21,
+       HDMI_APB_CLK_ROOT               = 22,
+       HDMI_AXI_CLK_ROOT               = 23,
+       GPU_AXI_CLK_ROOT                = 24,
+       GPU_AHB_CLK_ROOT                = 25,
+       NOC_CLK_ROOT                    = 26,
+       NOC_IO_CLK_ROOT                 = 27,
+       ML_AXI_CLK_ROOT                 = 28,
+       ML_AHB_CLK_ROOT                 = 29,
+       AHB_CLK_ROOT                    = 32,
+       IPG_CLK_ROOT                    = 33,
+       AUDIO_AHB_CLK_ROOT              = 34,
+       MIPI_DSI_ESC_RX_CLK_ROOT        = 36,
+       MEDIA_DISP2_CLK_ROOT            = 38,
+       DRAM_SEL_CFG                    = 48,
+       CORE_SEL_CFG                    = 49,
+       DRAM_ALT_CLK_ROOT               = 64,
+       DRAM_APB_CLK_ROOT               = 65,
+       VPU_G1_CLK_ROOT                 = 66,
+       VPU_G2_CLK_ROOT                 = 67,
+       CAN1_CLK_ROOT                   = 68,
+       CAN2_CLK_ROOT                   = 69,
+       PCIE_PHY_CLK_ROOT               = 71,
+       PCIE_AUX_CLK_ROOT               = 72,
+       I2C5_CLK_ROOT                   = 73,
+       I2C6_CLK_ROOT                   = 74,
+       SAI1_CLK_ROOT                   = 75,
+       SAI2_CLK_ROOT                   = 76,
+       SAI3_CLK_ROOT                   = 77,
+       SAI4_CLK_ROOT                   = 78,
+       SAI5_CLK_ROOT                   = 79,
+       SAI6_CLK_ROOT                   = 80,
+       ENET_QOS_CLK_ROOT               = 81,
+       ENET_QOS_TIMER_CLK_ROOT         = 82,
+       ENET_REF_CLK_ROOT               = 83,
+       ENET_TIMER_CLK_ROOT             = 84,
+       ENET_PHY_REF_CLK_ROOT           = 85,
+       NAND_CLK_ROOT                   = 86,
+       QSPI_CLK_ROOT                   = 87,
+       USDHC1_CLK_ROOT                 = 88,
+       USDHC2_CLK_ROOT                 = 89,
+       I2C1_CLK_ROOT                   = 90,
+       I2C2_CLK_ROOT                   = 91,
+       I2C3_CLK_ROOT                   = 92,
+       I2C4_CLK_ROOT                   = 93,
+       UART1_CLK_ROOT                  = 94,
+       UART2_CLK_ROOT                  = 95,
+       UART3_CLK_ROOT                  = 96,
+       UART4_CLK_ROOT                  = 97,
+       USB_CORE_REF_CLK_ROOT           = 98,
+       USB_PHY_REF_CLK_ROOT            = 99,
+       GIC_CLK_ROOT                    = 100,
+       ECSPI1_CLK_ROOT                 = 101,
+       ECSPI2_CLK_ROOT                 = 102,
+       PWM1_CLK_ROOT                   = 103,
+       PWM2_CLK_ROOT                   = 104,
+       PWM3_CLK_ROOT                   = 105,
+       PWM4_CLK_ROOT                   = 106,
+       GPT1_CLK_ROOT                   = 107,
+       GPT2_CLK_ROOT                   = 108,
+       GPT3_CLK_ROOT                   = 109,
+       GPT4_CLK_ROOT                   = 110,
+       GPT5_CLK_ROOT                   = 111,
+       GPT6_CLK_ROOT                   = 112,
+       TRACE_CLK_ROOT                  = 113,
+       WDOG_CLK_ROOT                   = 114,
+       WRCLK_CLK_ROOT                  = 115,
+       IPP_DO_CLKO1                    = 116,
+       IPP_DO_CLKO2                    = 117,
+       HDMI_FDCC_TST_CLK_ROOT          = 118,
+       HDMI_27M_CLK_ROOT               = 119,
+       HDMI_REF_266M_CLK_ROOT          = 120,
+       USDHC3_CLK_ROOT                 = 121,
+       MEDIA_CAM1_PIX_CLK_ROOT         = 122,
+       MEDIA_MIPI_PHY1_REF_CLK_ROOT    = 123,
+       MEDIA_DISP1_PIX_CLK_ROOT        = 124,
+       MEDIA_CAM2_PIX_CLK_ROOT         = 125,
+       MEDIA_LDB_CLK_ROOT      = 126,
+       MEMREPAIR_CLK_ROOT      = 127,
+       MEDIA_MIPI_TEST_BYTE_CLK        = 130,
+       ECSPI3_CLK_ROOT                 = 131,
+       PDM_CLK_ROOT                    = 132,
+       VPU_VC8000E_CLK_ROOT            = 133,
+       SAI7_CLK_ROOT                   = 134,
+       CLK_ROOT_MAX,
+};
+#elif defined(CONFIG_IMX8MN)
 enum clk_root_index {
        ARM_A53_CLK_ROOT                = 0,
        ARM_M7_CLK_ROOT                 = 1,
@@ -284,6 +386,7 @@ enum clk_ccgr_index {
        CCGR_GPT2 = 17,
        CCGR_GPT3 = 18,
        CCGR_GPT4 = 19,
+       CCGR_AAM_8MP = 20,
        CCGR_GPT5 = 20,
        CCGR_GPT6 = 21,
        CCGR_HS = 22,
@@ -315,7 +418,9 @@ enum clk_ccgr_index {
        CCGR_RAWNAND = 48,
        CCGR_RDC = 49,
        CCGR_ROM = 50,
+       CCGR_I2C5_8MP = 51,
        CCGR_SAI1 = 51,
+       CCGR_I2C6_8MP = 52,
        CCGR_SAI2 = 52,
        CCGR_SAI3 = 53,
        CCGR_SAI4 = 54,
@@ -327,13 +432,16 @@ enum clk_ccgr_index {
        CCGR_SEC_DEBUG = 60,
        CCGR_SEMA1 = 61,
        CCGR_SEMA2 = 62,
+       CCGR_IRQ_STEER_8MP = 63,
        CCGR_SIM_DISPLAY = 63,
        CCGR_SIM_ENET = 64,
        CCGR_SIM_M = 65,
        CCGR_SIM_MAIN = 66,
        CCGR_SIM_S = 67,
        CCGR_SIM_WAKEUP = 68,
+       CCGR_GPU2D_8MP = 69,
        CCGR_SIM_HSIO = 69,
+       CCGR_GPU3D_8MP = 70,
        CCGR_SIM_VPU = 70,
        CCGR_SNVS = 71,
        CCGR_TRACE = 72,
@@ -342,6 +450,7 @@ enum clk_ccgr_index {
        CCGR_UART3 = 75,
        CCGR_UART4 = 76,
        CCGR_USB_MSCALE_PL301 = 77,
+       CCGR_USB_PHY_8MP = 79,
        CCGR_GPU3D = 79,
        CCGR_USDHC1 = 81,
        CCGR_USDHC2 = 82,
@@ -361,6 +470,7 @@ enum clk_ccgr_index {
        CCGR_PLL = 97,
        CCGR_TEMP_SENSOR = 98,
        CCGR_VPUMIX_BUS = 99,
+       CCGR_SAI7 = 101,
        CCGR_GPU2D = 102,
        CCGR_MAX
 };

diff --git a/arch/arm/mach-imx/imx8m/Makefile b/arch/arm/mach-imx/imx8m/Makefile
index db4ba30c24dde67001544b14536b4c8ce35dc669..d9dee894aae17c89badcc6056f33a443ca0dc6b0 100644 (file)
--- a/arch/arm/mach-imx/imx8m/Makefile
+++ b/arch/arm/mach-imx/imx8m/Makefile
@@ -5,4 +5,4 @@
 obj-y += lowlevel_init.o
 obj-y += clock_slice.o soc.o
 obj-$(CONFIG_IMX8MQ) += clock_imx8mq.o
-obj-$(CONFIG_IMX8MM)$(CONFIG_IMX8MN) += clock_imx8mm.o
+obj-$(CONFIG_IMX8MM)$(CONFIG_IMX8MN)$(CONFIG_IMX8MP) += clock_imx8mm.o

diff --git a/arch/arm/mach-imx/imx8m/clock_slice.c b/arch/arm/mach-imx/imx8m/clock_slice.c
index 09c5615004b4b8e22f487771c547a6ee95439a50..31925ccaba9fb94a35b69515e7fd4f925151e09f 100644 (file)
--- a/arch/arm/mach-imx/imx8m/clock_slice.c
+++ b/arch/arm/mach-imx/imx8m/clock_slice.c
@@ -538,6 +538,278 @@ static struct clk_root_map root_array[] = {
         {DRAM_PLL1_CLK}
        },
 };
+#elif defined(CONFIG_IMX8MP)
+static struct clk_root_map root_array[] = {
+       {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
+        {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
+         SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
+         SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
+       },
+       {ARM_M7_CLK_ROOT, CORE_CLOCK_SLICE, 1,
+        {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
+         VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+         AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
+       },
+       {ML_CLK_ROOT, CORE_CLOCK_SLICE, 2,
+        {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
+         VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+         AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
+       },
+       {HSIO_AXI_CLK_ROOT, CORE_CLOCK_SLICE, 7,
+        {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
+         SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK, EXT_CLK_2,
+         EXT_CLK_4, AUDIO_PLL2_CLK}
+       },
+       {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
+        {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
+         SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK, AUDIO_PLL1_CLK,
+         VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
+       },
+       {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
+        {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+         SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK, AUDIO_PLL1_CLK,
+         VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
+       },
+       {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
+        {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+         SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
+         SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
+       },
+       {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
+        {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
+         SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
+         AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+       },
+       {NOC_IO_CLK_ROOT, BUS_CLOCK_SLICE, 11,
+        {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
+         SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
+         AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+       },
+       {ML_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 12,
+        {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
+         SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+         AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+       },
+       {ML_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 13,
+        {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
+         SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+         AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+       },
+       {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
+        {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
+         SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
+         SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
+       },
+       {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
+        {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
+         SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
+         SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
+       },
+       {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
+        {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+         SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+         SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+       },
+       {MEMREPAIR_CLK_ROOT, IP_CLOCK_SLICE, 6,
+        {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+         SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
+         SYSTEM_PLL1_133M_CLK}
+       },
+       {I2C5_CLK_ROOT, IP_CLOCK_SLICE, 9,
+        {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+         SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
+         SYSTEM_PLL1_133M_CLK}
+       },
+       {I2C6_CLK_ROOT, IP_CLOCK_SLICE, 10,
+        {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+         SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
+         SYSTEM_PLL1_133M_CLK}
+       },
+       {ENET_QOS_CLK_ROOT, IP_CLOCK_SLICE, 17,
+        {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
+         SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+         AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
+       },
+       {ENET_QOS_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 18,
+        {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1,
+         EXT_CLK_2, EXT_CLK_3, EXT_CLK_4, VIDEO_PLL_CLK}
+       },
+       {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
+        {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
+         SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+         AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
+       },
+       {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
+        {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1,
+         EXT_CLK_2, EXT_CLK_3, EXT_CLK_4, VIDEO_PLL_CLK}
+       },
+       {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
+        {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
+         SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
+         VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+       },
+       {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
+        {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
+         SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
+         SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
+       },
+       {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
+        {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_333M_CLK,
+         SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
+         SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
+       },
+       {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
+        {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
+         SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
+         SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
+       },
+       {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
+        {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
+         SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
+         SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
+       },
+       {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
+        {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+         SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+         AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+       },
+       {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
+        {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+         SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+         AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+       },
+       {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
+        {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+         SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+         AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+       },
+       {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
+        {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+         SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+         AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+       },
+       {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
+        {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
+         SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
+         EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+       },
+       {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
+        {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
+         SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
+         EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+       },
+       {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
+        {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
+         SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
+         EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+       },
+       {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
+        {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
+         SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
+         EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+       },
+       {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
+        {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
+         SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
+         EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+       },
+       {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
+        {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+         SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
+         EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+       },
+       {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
+        {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+         SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+         SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+       },
+       {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
+        {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+         SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+         SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+       },
+       {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
+        {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+         SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
+         SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+       },
+       {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
+        {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+         SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
+         SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+       },
+       {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
+        {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+         SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
+         SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+       },
+       {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
+        {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+         SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
+         SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+       },
+       {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
+        {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+         SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+         SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
+       },
+       {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
+        {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+         SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+         SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
+       },
+       {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
+        {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+         SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+         SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
+       },
+       {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
+        {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+         SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+         SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
+       },
+       {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
+        {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+         SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+         SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
+       },
+       {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
+        {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+         SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+         SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
+       },
+       {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
+        {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
+         VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
+         SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
+       },
+       {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
+        {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
+         VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
+         SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
+       },
+       {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
+        {OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
+         SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
+         SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
+       },
+       {USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57,
+        {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
+         SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
+         SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
+       },
+       {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
+        {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+         SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+         SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+       },
+       {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
+        {DRAM_PLL1_CLK}
+       },
+       {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
+        {DRAM_PLL1_CLK}
+       },
+};
 #endif
 
 static int select(enum clk_root_index clock_id)