armv8/fsl-lsch3: Fix TCR_EL3 for the final MMU setup.

When final MMU table is setup in DDR, TCR attributes must match
those of the memroy for cacheability and shareability.

Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index 52bc73177fc66f1a43a642a97d75f475e5ef3a75..d02c0beef9f231f845ce052b1152e89abf0ba7a3 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -82,6 +82,12 @@ void cpu_name(char *name)
                        TCR_ORGN_NC             | \
                        TCR_IRGN_NC             | \
                        TCR_T0SZ(LSCH3_VA_BITS))
+#define LSCH3_TCR_FINAL        (TCR_TG0_4K             | \
+                       TCR_EL2_PS_40BIT        | \
+                       TCR_SHARED_OUTER        | \
+                       TCR_ORGN_WBWA           | \
+                       TCR_IRGN_WBWA           | \
+                       TCR_T0SZ(LSCH3_VA_BITS))
 
 /*
  * Final MMU
@@ -266,21 +272,8 @@ static inline void final_mmu_setup(void)
 
        /* point TTBR to the new table */
        el = current_el();
-       asm volatile("dsb sy");
-       if (el == 1) {
-               asm volatile("msr ttbr0_el1, %0"
-                            : : "r" ((u64)level0_table) : "memory");
-       } else if (el == 2) {
-               asm volatile("msr ttbr0_el2, %0"
-                            : : "r" ((u64)level0_table) : "memory");
-       } else if (el == 3) {
-               asm volatile("msr ttbr0_el3, %0"
-                            : : "r" ((u64)level0_table) : "memory");
-       } else {
-               hang();
-       }
-       asm volatile("isb");
-
+       set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR_FINAL,
+                         MEMORY_ATTRIBUTES);
        /*
         * MMU is already enabled, just need to invalidate TLB to load the
         * new table. The new table is compatible with the current table, if