tegra: pwm: Allow the clock rate to be left as is

When enabling a PWM, allow the existing clock rate and source to stand
unchanged.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/include/asm/arch-tegra/pwm.h b/arch/arm/include/asm/arch-tegra/pwm.h
index 8e7397d0e5acd9f8a0e06dfcafc88fc568769571..92dced448abff94e242b66ae498f4bcc7a70e11e 100644 (file)
--- a/arch/arm/include/asm/arch-tegra/pwm.h
+++ b/arch/arm/include/asm/arch-tegra/pwm.h
@@ -31,7 +31,7 @@ struct pwm_ctlr {
  * Program the PWM with the given parameters.
  *
  * @param channel      PWM channel to update
- * @param rate         Clock rate to use for PWM
+ * @param rate         Clock rate to use for PWM, or 0 to leave alone
  * @param pulse_width  high pulse width: 0=always low, 1=1/256 pulse high,
  *                     n = n/256 pulse high
  * @param freq_divider frequency divider value (1 to use rate as is)

diff --git a/arch/arm/mach-tegra/pwm.c b/arch/arm/mach-tegra/pwm.c
index 86642004309265a044ff012c15da168e2559d887..1c38fc1784938b41e67e7b4989f87ced19e40188 100644 (file)
--- a/arch/arm/mach-tegra/pwm.c
+++ b/arch/arm/mach-tegra/pwm.c
@@ -24,7 +24,10 @@ void pwm_enable(unsigned channel, int rate, int pulse_width, int freq_divider)
        assert(channel < PWM_NUM_CHANNELS);
 
        /* TODO: Can we use clock_adjust_periph_pll_div() here? */
-       clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, rate);
+       if (rate) {
+               clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ,
+                                      rate);
+       }
 
        reg = PWM_ENABLE_MASK;
        reg |= pulse_width << PWM_WIDTH_SHIFT;