ARM: zynq: Add DTSes for mini qspi configurations

Mini U-Boot is running out of OCM and it's only purpose is to program non
volatile memories. There are different configurations which qspi can be
that's why describe them via DT.
DT binding is already approved that's why there is no reason not to add it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/28b3cdd7e91b2b4c3c36d0bf65aa5bac042f248c.1698329087.git.michal.simek@amd.com

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 55aceb51cdb00eb3f10477a0e886d081b0b6f930..c7e03c5364329398e0a777f42f90d175d8c71436 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -376,6 +376,12 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
        zynq-cse-nand.dtb \
        zynq-cse-nor.dtb \
        zynq-cse-qspi-single.dtb \
+       zynq-cse-qspi-parallel.dtb \
+       zynq-cse-qspi-stacked.dtb \
+       zynq-cse-qspi-x1-single.dtb \
+       zynq-cse-qspi-x1-stacked.dtb \
+       zynq-cse-qspi-x2-single.dtb \
+       zynq-cse-qspi-x2-stacked.dtb \
        zynq-dlc20-rev1.0.dtb \
        zynq-microzed.dtb \
        zynq-minized.dtb \

diff --git a/arch/arm/dts/zynq-cse-qspi-parallel.dts b/arch/arm/dts/zynq-cse-qspi-parallel.dts
new file mode 100644 (file)
index 0000000..afa6348
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi-parallel.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE QSPI Quad Parallel DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynq-cse-qspi.dtsi"
+
+/ {
+       model = "Zynq CSE QSPI PARALLEL Board";
+};
+
+&qspi {
+       num-cs = <2>;
+};
+
+&flash0 {
+       reg = <0>, <1>;
+       parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */
+       spi-rx-bus-width = <4>;
+};

diff --git a/arch/arm/dts/zynq-cse-qspi-stacked.dts b/arch/arm/dts/zynq-cse-qspi-stacked.dts
new file mode 100644 (file)
index 0000000..47859f7
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi-stacked.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE QSPI Quad Stacked DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynq-cse-qspi.dtsi"
+
+/ {
+       model = "Zynq CSE QSPI STACKED Board";
+};
+
+&qspi {
+       num-cs = <2>;
+};
+
+&flash0 {
+       reg = <0>, <1>;
+       stacked-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */
+       spi-rx-bus-width = <4>;
+};

diff --git a/arch/arm/dts/zynq-cse-qspi-x1-single.dts b/arch/arm/dts/zynq-cse-qspi-x1-single.dts
new file mode 100644 (file)
index 0000000..c14fb42
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi-x1-single.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE QSPI x1 Single DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynq-cse-qspi.dtsi"
+
+/ {
+       model = "Zynq CSE QSPI X1 SINGLE Board";
+};
+
+&flash0 {
+       spi-rx-bus-width = <1>;
+};

diff --git a/arch/arm/dts/zynq-cse-qspi-x1-stacked.dts b/arch/arm/dts/zynq-cse-qspi-x1-stacked.dts
new file mode 100644 (file)
index 0000000..0f4d414
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi-x1-stacked.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE QSPI x1 Stacked DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynq-cse-qspi.dtsi"
+
+/ {
+       model = "Zynq CSE QSPI X1 STACKED Board";
+};
+
+&qspi {
+       num-cs = <2>;
+};
+
+&flash0 {
+       reg = <0>, <1>;
+       stacked-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */
+       spi-rx-bus-width = <1>;
+};

diff --git a/arch/arm/dts/zynq-cse-qspi-x2-single.dts b/arch/arm/dts/zynq-cse-qspi-x2-single.dts
new file mode 100644 (file)
index 0000000..11be063
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi-x2-single.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE QSPI x2 Single DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynq-cse-qspi.dtsi"
+
+/ {
+       model = "Zynq CSE QSPI X2 SINGLE Board";
+};
+
+&flash0 {
+       spi-rx-bus-width = <2>;
+};

diff --git a/arch/arm/dts/zynq-cse-qspi-x2-stacked.dts b/arch/arm/dts/zynq-cse-qspi-x2-stacked.dts
new file mode 100644 (file)
index 0000000..d1b42e9
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi-x2-stacked.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE QSPI x2 Stacked DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynq-cse-qspi.dtsi"
+
+/ {
+       model = "Zynq CSE QSPI X2 STACKED Board";
+};
+
+&qspi {
+       num-cs = <2>;
+};
+
+&flash0 {
+       reg = <0>, <1>;
+       stacked-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */
+       spi-rx-bus-width = <2>;
+};