Tegra: Fix MSELECT clock divisors for T30/T114.

A comparison of registers between our internal NV U-Boot and
u-boot-tegra/next showed some discrepancies in the MSELECT
clock divisor programming. T20 doesn't have a MSELECT clk src reg.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>

diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c
index 6a94179d4aa84290c1b929a301d4c526521e6716..51ecff794fb7f1cf85983a91ff671fd937a63e32 100644 (file)
--- a/arch/arm/cpu/arm720t/tegra114/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra114/cpu.c
@@ -170,15 +170,13 @@ void t114_init_clocks(void)
        clock_set_enable(PERIPH_ID_MC1, 1);
        clock_set_enable(PERIPH_ID_DVFS, 1);
 
-       /* Switch MSELECT clock to PLLP (00) */
-       clock_ll_set_source(PERIPH_ID_MSELECT, 0);
-
        /*
-        * Clock divider request for 102MHz would setup MSELECT clock as
-        * 102MHz for PLLP base 408MHz
+        * Set MSELECT clock source as PLLP (00), and ask for a clock
+        * divider that would set the MSELECT clock at 102MHz for a
+        * PLLP base of 408MHz.
         */
        clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0,
-               (NVBL_PLLP_KHZ/102000));
+               CLK_DIVIDER(NVBL_PLLP_KHZ, 102000));
 
        /* I2C5 (DVC) gets CLK_M and a divisor of 17 */
        clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16);

diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c
index dedcdd9b08ce4ca58b8df41fa88eb2c9ea6c0b81..e16235748449c61bd54715643dd7ee9d278485c5 100644 (file)
--- a/arch/arm/cpu/arm720t/tegra30/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra30/cpu.c
@@ -110,8 +110,8 @@ void t30_init_clocks(void)
        reset_set_enable(PERIPH_ID_MSELECT, 1);
        clock_set_enable(PERIPH_ID_MSELECT, 1);
 
-       /* Switch MSELECT clock to PLLP (00) */
-       clock_ll_set_source(PERIPH_ID_MSELECT, 0);
+       /* Switch MSELECT clock to PLLP (00) and use a divisor of 2 */
+       clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, 2);
 
        /*
         * Our high-level clock routines are not available prior to