Add new board based on the Toradex Verdin iMX8M Mini SoM, the MX8Menlo.
The board is a compatible replacement for i.MX53 M53Menlo and features
USB, multiple UARTs, ethernet, LEDs, SD and eMMC.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Max Krummenacher <max.krummenacher@toradex.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
imx8mm-icore-mx8mm-edimm2.2.dtb \
imx8mm-kontron-n801x-s.dtb \
imx8mm-kontron-n801x-s-lvds.dtb \
+ imx8mm-mx8menlo.dtb \
imx8mm-venice.dtb \
imx8mm-venice-gw71xx-0x.dtb \
imx8mm-venice-gw72xx-0x.dtb \
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright 2021-2022 Marek Vasut <marex@denx.de>
+ */
+#include "imx8mm-verdin-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ aliases {
+ /delete-property/ eeprom1;
+ /delete-property/ eeprom2;
+ usbphy0 = &usbphynop1;
+ usbphy1 = &usbphynop2;
+ };
+};
+
+&i2c4 {
+ /delete-node/ codec@1a;
+};
+
+&pinctrl_uart1 {
+ /delete-property/ u-boot,dm-spl;
+};
+
+&pinctrl_uart2 {
+ u-boot,dm-spl;
+};
+
+&uart1 {
+ /delete-property/ u-boot,dm-spl;
+};
+
+&uart2 {
+ u-boot,dm-spl;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright 2021-2022 Marek Vasut <marex@denx.de>
+ */
+
+#include "imx8mm-verdin.dts"
+
+/ {
+ model = "MENLO MX8MM EMBEDDED DEVICE";
+ compatible = "menlo,mx8menlo",
+ "toradex,verdin-imx8mm",
+ "fsl,imx8mm";
+
+ /delete-node/ gpio-keys;
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led>;
+
+ user1 {
+ label = "TestLed601";
+ gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ };
+
+ user2 {
+ label = "TestLed602";
+ gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ beeper {
+ compatible = "gpio-beeper";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_beeper>;
+ gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&ecspi1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ /* CAN controller on the baseboard */
+ canfd: can@0 {
+ compatible = "microchip,mcp2518fd";
+ clocks = <&clk20m>;
+ gpio-controller;
+ interrupt-parent = <&gpio1>;
+ interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
+ reg = <0>;
+ spi-max-frequency = <2000000>;
+ status = "okay";
+ };
+
+};
+
+&ecspi2 {
+ pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_gpio1>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, <&gpio3 4 GPIO_ACTIVE_LOW>;
+ status = "disabled";
+};
+
+ðphy0 {
+ max-speed = <100>;
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&flexspi {
+ status = "okay";
+
+ flash@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <66000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ };
+};
+
+&gpio1 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpio2 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpio3 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "DISP_reset", "KBD_intI",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpio4 {
+ /*
+ * CPLD_D[n] is ARM_CPLD[n] in schematic
+ * CPLD_int is SA_INTERRUPT in schematic
+ * CPLD_reset is RESET_SOFT in schematic
+ */
+ gpio-line-names =
+ "CPLD_D[1]", "CPLD_int", "CPLD_reset", "",
+ "", "CPLD_D[0]", "", "",
+ "", "", "", "CPLD_D[2]",
+ "CPLD_D[3]", "CPLD_D[4]", "CPLD_D[5]", "CPLD_D[6]",
+ "CPLD_D[7]", "", "", "",
+ "", "", "", "",
+ "", "", "", "KBD_intK",
+ "", "", "", "";
+};
+
+&gpio5 {
+ gpio-line-names =
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpio_expander_21 {
+ status = "okay";
+};
+
+&i2c1 {
+ /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
+ clock-frequency = <100000>;
+};
+
+&i2c2 {
+ /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
+ clock-frequency = <100000>;
+};
+
+&i2c3 {
+ /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&i2c4 {
+ /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
+ clock-frequency = <100000>;
+ /delete-node/ bridge@2c;
+ /delete-node/ hwmon@40;
+ /delete-node/ hdmi@48;
+ /delete-node/ touch@4a;
+ /delete-node/ hwmontemp@4f;
+ /delete-node/ eeprom@50;
+ /delete-node/ eeprom@57;
+};
+
+&iomuxc {
+ pinctrl-0 = <&pinctrl_gpio7>, <&pinctrl_gpio_hog1>,
+ <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>;
+
+ pinctrl_beeper: beepergrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1c4
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x4
+ MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x4
+ MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1c4
+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x1c4
+ >;
+ };
+
+ pinctrl_led: ledgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c4
+ MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x1c4
+ >;
+ };
+
+ pinctrl_uart4_rts: uart4rtsgrp {
+ fsl,pins = <
+ /* SODIMM 222 */
+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184
+ >;
+ };
+};
+
+&pinctrl_gpio1 {
+ fsl,pins = <
+ /* SODIMM 206 */
+ MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x1c4
+ >;
+};
+
+&pinctrl_gpio_hog1 {
+ fsl,pins = <
+ /* SODIMM 88 */
+ MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4
+ /* CPLD_int */
+ MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4
+ /* CPLD_reset */
+ MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4
+ /* SODIMM 94 */
+ MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4
+ /* SODIMM 96 */
+ MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4
+ /* CPLD_D[7] */
+ MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x1c4
+ /* CPLD_D[6] */
+ MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1c4
+ /* CPLD_D[5] */
+ MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x1c4
+ /* CPLD_D[4] */
+ MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x1c4
+ /* CPLD_D[3] */
+ MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c4
+ /* CPLD_D[2] */
+ MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c4
+ /* CPLD_D[1] */
+ MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c4
+ /* CPLD_D[0] */
+ MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x1c4
+ /* KBD_intK */
+ MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1c4
+ /* DISP_reset */
+ MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x1c4
+ /* KBD_intI */
+ MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x1c4
+ /* SODIMM 46 */
+ MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x1c4
+ >;
+};
+
+&pinctrl_uart1 {
+ fsl,pins = <
+ /* SODIMM 149 */
+ MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1c4
+ /* SODIMM 147 */
+ MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1c4
+ /* SODIMM 210 */
+ MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x1c4
+ /* SODIMM 212 */
+ MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x1c4
+ >;
+};
+
+®_usb_otg1_vbus {
+ /delete-property/ enable-active-high;
+ gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
+};
+
+®_usb_otg2_vbus {
+ /delete-property/ enable-active-high;
+ gpio = <&gpio1 14 GPIO_ACTIVE_LOW>;
+};
+
+&sai2 {
+ status = "disabled";
+};
+
+&uart1 {
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart2 {
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-0 = <&pinctrl_uart4 &pinctrl_uart4_rts>;
+ linux,rs485-enabled-at-boot-time;
+ rts-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "gadget";
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usdhc2 {
+ status = "okay";
+};
* i.Core MX8M Mini needs to mount on top of this Carrier board
for creating complete i.Core MX8M Mini C.TOUCH 2.0 board.
+config TARGET_IMX8MM_MX8MENLO
+ bool "Support i.MX8M Mini MX8Menlo board based on Toradex Verdin SoM"
+ select BINMAN
+ select IMX8MM
+ select SUPPORT_SPL
+ select IMX8M_LPDDR4
+
config TARGET_IMX8MM_VENICE
bool "Support Gateworks Venice iMX8M Mini module"
select BINMAN
source "board/google/imx8mq_phanbell/Kconfig"
source "board/kontron/pitx_imx8m/Kconfig"
source "board/kontron/sl-mx8mm/Kconfig"
+source "board/menlo/mx8menlo/Kconfig"
source "board/phytec/phycore_imx8mm/Kconfig"
source "board/phytec/phycore_imx8mp/Kconfig"
source "board/ronetix/imx8mq-cm/Kconfig"
--- /dev/null
+if TARGET_IMX8MM_MX8MENLO
+
+config SYS_BOARD
+ default "mx8menlo"
+
+config SYS_VENDOR
+ default "menlo"
+
+config SYS_CONFIG_NAME
+ default "imx8mm-mx8menlo"
+
+config TDX_CFG_BLOCK
+ default y
+
+config TDX_CFG_BLOCK_EXTRA
+ default y
+
+config TDX_HAVE_MMC
+ default y
+
+config TDX_HAVE_EEPROM_EXTRA
+ default y
+
+config TDX_CFG_BLOCK_DEV
+ default "0"
+
+config TDX_CFG_BLOCK_PART
+ default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+ default "-512"
+
+config IMX_CONFIG
+ default "board/toradex/verdin-imx8mm/imximage.cfg"
+
+source "board/toradex/common/Kconfig"
+
+endif
--- /dev/null
+MX8MENLO BOARD
+M: Marek Vasut <marex@denx.de>
+M: Olaf Mandel <o.mandel@menlosystems.com>
+S: Maintained
+F: board/menlo/mx8menlo/
+F: include/configs/imx8mm-mx8menlo.h
+F: configs/imx8mm-mx8menlo_defconfig
--- /dev/null
+#
+# Menlosystems MX8Menlo
+# Copyright (C) 2021-2022 Marek Vasut <marex@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx8menlo.o
+
+obj-y += ../../toradex/verdin-imx8mm/verdin-imx8mm.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += ../../toradex/verdin-imx8mm/spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += ../../toradex/verdin-imx8mm/lpddr4_timing.o
+endif
+
+# Common for all Toradex modules
+ifeq ($(CONFIG_SPL_BUILD),y)
+# Necessary to create built-in.o
+obj- := __dummy__.o
+else
+obj-$(CONFIG_TDX_CFG_BLOCK) += ../../toradex/common/tdx-cfg-block.o
+obj-y += ../../toradex/common/tdx-common.o
+obj-y += ../../toradex/common/tdx-eeprom.o
+endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021-2022 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <spl.h>
+
+#define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+/* Verdin UART_3, Console/Debug UART */
+static iomux_v3_cfg_t const uart_pads[] = {
+ IMX8MM_PAD_SAI3_TXFS_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IMX8MM_PAD_SAI3_TXC_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+ IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+#define SNVS_BASE_ADDR 0x30370000
+#define SNVS_LPSR 0x4c
+#define SNVS_LPLVDR 0x64
+#define SNVS_LPPGDR_INIT 0x41736166
+
+static void setup_snvs(void)
+{
+ /* Enable SNVS clock */
+ clock_enable(CCGR_SNVS, 1);
+ /* Initialize glitch detect */
+ writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
+ /* Clear interrupt status */
+ writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
+}
+
+void board_early_init(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+ set_wdog_reset(wdog);
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+ init_uart_clk(1);
+
+ setup_snvs();
+}
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xFFFFDE00
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-mx8menlo"
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_MX8MENLO=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_BOOTCOUNT_BOOTLIMIT=3
+CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
+CONFIG_SPL=y
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_ENV_OFFSET_REDUND=0xFFFFDE00
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="mmc partconf 0 distro_bootpart && load ${devtype} ${devnum}:${distro_bootpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset"
+CONFIG_DEFAULT_FDT_FILE="imx8mm-mx8menlo.dtb"
+CONFIG_LOG=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="Verdin iMX8MM # "
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_BOOTCOUNT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_UUID=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_BTRFS=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="FEC"
+CONFIG_VERSION_VARIABLE=y
+CONFIG_IP_DEFRAG=y
+CONFIG_TFTP_BLOCKSIZE=4096
+CONFIG_SPL_DM=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MM=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_GPIO_HOG=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_OF_LIBFDT_OVERLAY=y
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021-2022 Marek Vasut <marex@denx.de>
+ */
+
+#ifndef __IMX8MM_MX8MENLO_H
+#define __IMX8MM_MX8MENLO_H
+
+#include <configs/verdin-imx8mm.h>
+
+/* Custom initial environment variables */
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ BOOTENV \
+ MEM_LAYOUT_ENV_SETTINGS \
+ "devtype=mmc\0" \
+ "devnum=1\0" \
+ "distro_bootpart=1\0" \
+ "altbootcmd=" \
+ "mmc partconf 0 mmcpart ; " \
+ "if test ${mmcpart} -eq 1 ; then " \
+ "mmc partconf 0 1 2 0 ; " \
+ "else " \
+ "mmc partconf 0 1 1 0 ; " \
+ "fi ; " \
+ "boot\0" \
+ "boot_file=fitImage\0" \
+ "console=ttymxc1\0" \
+ "fdt_addr=0x43000000\0" \
+ "initrd_addr=0x43800000\0" \
+ "kernel_image=fitImage\0"
+
+#undef CONFIG_MXC_UART_BASE
+#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
+
+#endif /* __IMX8MM_MX8MENLO_H */
projects / u-boot.git / commitdiff
