ti: wdt: common: Make the wdt IP defines common for the TI platform

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index dbed7764aa83a9b143ca8faa1240814cd1bf5f5c..54f449f6e6960d2484b9f7d448b40d6e9d6038ed 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -66,29 +66,9 @@
 #define PRM_RSTCTRL_RESET              0x01
 #define PRM_RSTST_WARM_RESET_MASK      0x232
 
-/*
- * Watchdog:
- * Using the prescaler, the OMAP watchdog could go for many
- * months before firing.  These limits work without scaling,
- * with the 60 second default assumed by most tools and docs.
- */
-#define TIMER_MARGIN_MAX       (24 * 60 * 60)  /* 1 day */
-#define TIMER_MARGIN_DEFAULT   60      /* 60 secs */
-#define TIMER_MARGIN_MIN       1
-
-#define PTV                    0       /* prescale */
-#define GET_WLDR_VAL(secs)     (0xffffffff - ((secs) * (32768/(1<<PTV))) + 1)
-#define WDT_WWPS_PEND_WCLR     BIT(0)
-#define WDT_WWPS_PEND_WLDR     BIT(2)
-#define WDT_WWPS_PEND_WTGR     BIT(3)
-#define WDT_WWPS_PEND_WSPR     BIT(4)
-
-#define WDT_WCLR_PRE           BIT(5)
-#define WDT_WCLR_PTV_OFF       2
-
 #ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
-
+#include <asm/ti-common/omap_wdt.h>
 
 #ifndef CONFIG_AM43XX
 /* Encapsulating core pll registers */
@@ -422,32 +402,6 @@ struct cm_rtc {
        unsigned int clkstctrl;         /* offset 0x4 */
 };
 
-/* Watchdog timer registers */
-struct wd_timer {
-       unsigned int resv1[4];
-       unsigned int wdtwdsc;   /* offset 0x010 */
-       unsigned int wdtwdst;   /* offset 0x014 */
-       unsigned int wdtwisr;   /* offset 0x018 */
-       unsigned int wdtwier;   /* offset 0x01C */
-       unsigned int wdtwwer;   /* offset 0x020 */
-       unsigned int wdtwclr;   /* offset 0x024 */
-       unsigned int wdtwcrr;   /* offset 0x028 */
-       unsigned int wdtwldr;   /* offset 0x02C */
-       unsigned int wdtwtgr;   /* offset 0x030 */
-       unsigned int wdtwwps;   /* offset 0x034 */
-       unsigned int resv2[3];
-       unsigned int wdtwdly;   /* offset 0x044 */
-       unsigned int wdtwspr;   /* offset 0x048 */
-       unsigned int resv3[1];
-       unsigned int wdtwqeoi;  /* offset 0x050 */
-       unsigned int wdtwqstar; /* offset 0x054 */
-       unsigned int wdtwqsta;  /* offset 0x058 */
-       unsigned int wdtwqens;  /* offset 0x05C */
-       unsigned int wdtwqenc;  /* offset 0x060 */
-       unsigned int resv4[39];
-       unsigned int wdt_unfr;  /* offset 0x100 */
-};
-
 /* Timer 32 bit registers */
 struct gptimer {
        unsigned int tidr;              /* offset 0x00 */

diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h
index 683d9053337fc201b9e2e80d280e8e682c8b61fa..d7c46605ddd6d11506e9a996d950892c3d33df64 100644 (file)
--- a/arch/arm/include/asm/arch-omap5/cpu.h
+++ b/arch/arm/include/asm/arch-omap5/cpu.h
@@ -18,6 +18,8 @@
 
 #ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
+#include <asm/ti-common/omap_wdt.h>
+
 struct gptimer {
        u32 tidr;               /* 0x00 r */
        u8 res1[0xc];

diff --git a/arch/arm/include/asm/ti-common/omap_wdt.h b/arch/arm/include/asm/ti-common/omap_wdt.h
new file mode 100644 (file)
index 0000000..b9f4c07
--- /dev/null
+++ b/arch/arm/include/asm/ti-common/omap_wdt.h
@@ -0,0 +1,60 @@
+/*
+ * omap_wdt.h
+ *
+ * OMAP Watchdog header file
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __OMAP_WDT_H__
+#define __OMAP_WDT_H__
+
+/*
+ * Watchdog:
+ * Using the prescaler, the OMAP watchdog could go for many
+ * months before firing.  These limits work without scaling,
+ * with the 60 second default assumed by most tools and docs.
+ */
+#define TIMER_MARGIN_MAX       (24 * 60 * 60)  /* 1 day */
+#define TIMER_MARGIN_DEFAULT   60      /* 60 secs */
+#define TIMER_MARGIN_MIN       1
+
+#define PTV                    0       /* prescale */
+#define GET_WLDR_VAL(secs)     (0xffffffff - ((secs) * (32768/(1<<PTV))) + 1)
+#define WDT_WWPS_PEND_WCLR     BIT(0)
+#define WDT_WWPS_PEND_WLDR     BIT(2)
+#define WDT_WWPS_PEND_WTGR     BIT(3)
+#define WDT_WWPS_PEND_WSPR     BIT(4)
+
+#define WDT_WCLR_PRE           BIT(5)
+#define WDT_WCLR_PTV_OFF       2
+
+/* Watchdog timer registers */
+struct wd_timer {
+       unsigned int resv1[4];
+       unsigned int wdtwdsc;   /* offset 0x010 */
+       unsigned int wdtwdst;   /* offset 0x014 */
+       unsigned int wdtwisr;   /* offset 0x018 */
+       unsigned int wdtwier;   /* offset 0x01C */
+       unsigned int wdtwwer;   /* offset 0x020 */
+       unsigned int wdtwclr;   /* offset 0x024 */
+       unsigned int wdtwcrr;   /* offset 0x028 */
+       unsigned int wdtwldr;   /* offset 0x02C */
+       unsigned int wdtwtgr;   /* offset 0x030 */
+       unsigned int wdtwwps;   /* offset 0x034 */
+       unsigned int resv2[3];
+       unsigned int wdtwdly;   /* offset 0x044 */
+       unsigned int wdtwspr;   /* offset 0x048 */
+       unsigned int resv3[1];
+       unsigned int wdtwqeoi;  /* offset 0x050 */
+       unsigned int wdtwqstar; /* offset 0x054 */
+       unsigned int wdtwqsta;  /* offset 0x058 */
+       unsigned int wdtwqens;  /* offset 0x05C */
+       unsigned int wdtwqenc;  /* offset 0x060 */
+       unsigned int resv4[39];
+       unsigned int wdt_unfr;  /* offset 0x100 */
+};
+
+#endif /* __OMAP_WDT_H__ */