arm: kirkwood: Pogoplug E02 : Convert Ethernet to Driver Model

The Pogoplug E02 board has the network chip Marvell 88E1116R. Convert
to Driver Model and use uclass mvgbe and the compatible driver M88E1118R
to bring up Ethernet.

- Add board_eth_init(), CONFIG_DM_ETH, and CONFIG_PHY_MARVELL
to bring up Ethernet.
- Currently, CONFIG_RESET_PHY_R symbol is used in
arch/arm/mach-kirkwood/include/mach/config.h for all Kirkwood
boards with mv8831116 PHY, with each board defines the function
reset_phy(). Undefine it for this board.
- As the result of the migration to Driver Model, this u-boot image has
grown substantially (about 100K, give or take). The old envs location
at 0x60000 (384k) is no longer possible. Move it to 0xC0000 (768K).
- Miscellaneous changes: Move constants to .c file and remove header file
board/cloudengines/pogo_e02/pogo_e02.h, use CONFIG_SYS_THUMB_BUILD to
keep u-boot image under 512K, use BIT macro, and cleanup comments.

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/board/cloudengines/pogo_e02/pogo_e02.c b/board/cloudengines/pogo_e02/pogo_e02.c
index 039fd6e3dd676097b11f44ed378c365e3e6e79db..59e1218b411a18fd5169bc0cf032c9ac351960c5 100644 (file)
--- a/board/cloudengines/pogo_e02/pogo_e02.c
+++ b/board/cloudengines/pogo_e02/pogo_e02.c
@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
+ * Copyright (C) 2022 Tony Dinh <mibodhi@gmail.com>
  * Copyright (C) 2012
  * David Purdy <david.c.purdy@gmail.com>
  *
@@ -12,16 +13,21 @@
 #include <common.h>
 #include <init.h>
 #include <log.h>
-#include <miiphy.h>
-#include <net.h>
+#include <netdev.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
 #include <asm/global_data.h>
-#include "pogo_e02.h"
+#include <linux/bitops.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* GPIO configuration */
+#define POGO_E02_OE_LOW                        (~(0))
+#define POGO_E02_OE_HIGH               (~(0))
+#define POGO_E02_OE_VAL_LOW            BIT(29)
+#define POGO_E02_OE_VAL_HIGH           0
+
 int board_early_init_f(void)
 {
        /*
@@ -64,6 +70,11 @@ int board_early_init_f(void)
        return 0;
 }
 
+int board_eth_init(struct bd_info *bis)
+{
+       return cpu_eth_init(bis);
+}
+
 int board_init(void)
 {
        /* Boot parameters address */
@@ -71,37 +82,3 @@ int board_init(void)
 
        return 0;
 }
-
-#ifdef CONFIG_RESET_PHY_R
-/* Configure and initialize PHY */
-void reset_phy(void)
-{
-       u16 reg;
-       u16 devadr;
-       char *name = "egiga0";
-
-       if (miiphy_set_current_dev(name))
-               return;
-
-       /* command to read PHY dev address */
-       if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
-               printf("Err..(%s) could not read PHY dev address\n", __func__);
-               return;
-       }
-
-       /*
-        * Enable RGMII delay on Tx and Rx for CPU port
-        * Ref: sec 4.7.2 of chip datasheet
-        */
-       miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
-       miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
-       reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
-       miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
-       miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
-
-       /* reset the phy */
-       miiphy_reset(name, devadr);
-
-       debug("88E1116 Initialized on %s\n", name);
-}
-#endif /* CONFIG_RESET_PHY_R */

diff --git a/board/cloudengines/pogo_e02/pogo_e02.h b/board/cloudengines/pogo_e02/pogo_e02.h
deleted file mode 100644 (file)
index c8397b4..0000000
--- a/board/cloudengines/pogo_e02/pogo_e02.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2012
- * David Purdy <david.c.purdy@gmail.com>
- *
- * Based on Kirkwood support:
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- */
-
-#ifndef __POGO_E02_H
-#define __POGO_E02_H
-
-/* GPIO configuration */
-#define POGO_E02_OE_LOW                                (~(0))
-#define POGO_E02_OE_HIGH                       (~(0))
-#define POGO_E02_OE_VAL_LOW                    (1 << 29)
-#define POGO_E02_OE_VAL_HIGH                   0
-
-/* PHY related */
-#define MV88E1116_LED_FCTRL_REG                        10
-#define MV88E1116_CPRSP_CR3_REG                        21
-#define MV88E1116_MAC_CTRL_REG                 21
-#define MV88E1116_PGADR_REG                    22
-#define MV88E1116_RGMII_TXTM_CTRL              (1 << 4)
-#define MV88E1116_RGMII_RXTM_CTRL              (1 << 5)
-
-#endif /* __POGO_E02_H */

diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig
index 10f08a515d967503cc200b5b570b5ee07a49dc66..7853cc7b24ed008b26b4286de5d7ff13b42d5737 100644 (file)
--- a/configs/pogo_e02_defconfig
+++ b/configs/pogo_e02_defconfig
@@ -2,13 +2,14 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_CPU_INIT=y
+CONFIG_SYS_THUMB_BUILD=y
 CONFIG_ARCH_KIRKWOOD=y
 CONFIG_SYS_KWD_CONFIG="board/cloudengines/pogo_e02/kwbimage.cfg"
 CONFIG_SYS_TEXT_BASE=0x600000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_TARGET_POGO_E02=y
 CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0x60000
+CONFIG_ENV_OFFSET=0xC0000
 CONFIG_DEFAULT_DEVICE_TREE="kirkwood-pogo_e02"
 CONFIG_IDENT_STRING="\nPogo E02"
 # CONFIG_SYS_MALLOC_F is not set
@@ -36,11 +37,14 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
 CONFIG_DM=y
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
+CONFIG_PHY_MARVELL=y
+CONFIG_DM_ETH=y
 CONFIG_MVGBE=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y

diff --git a/include/configs/pogo_e02.h b/include/configs/pogo_e02.h
index 3e94125cb35f1d47960a2b0f25078c7f2d9611be..51c802f2b316ccba9c3021cb328cc8be0e23d2a3 100644 (file)
--- a/include/configs/pogo_e02.h
+++ b/include/configs/pogo_e02.h
@@ -14,10 +14,6 @@
 
 #include "mv-common.h"
 
-/*
- *  Environment variables configurations
- */
-
 /*
  * Default environment variables
  */
@@ -33,13 +29,10 @@
 /*
  * Ethernet Driver configuration
  */
-#ifdef CONFIG_CMD_NET
 #define CONFIG_MVGBE_PORTS     {1, 0}  /* enable port 0 only */
 #define CONFIG_PHY_BASE_ADR    0
-#endif /* CONFIG_CMD_NET */
-
-/*
- * File system
- */
+#ifdef CONFIG_RESET_PHY_R
+#undef CONFIG_RESET_PHY_R      /* remove legacy reset_phy() */
+#endif
 
 #endif /* _CONFIG_POGO_E02_H */