Convert CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS et al to Kconfig

This converts the following to Kconfig:
   CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
   CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS

And we remove the entries from the README for a number of already
converted items.

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/README b/README
index 6b6f7227336a1fff884e755ed59cdebdec371881..ebfdced4a725384a655423b7d9bc527a996e4961 100644 (file)
--- a/README
+++ b/README
@@ -363,68 +363,17 @@ The following options need to be configured:
                CONFIG_SYS_FSL_DDR_ADDR
                Freescale DDR memory-mapped register base.
 
-               CONFIG_SYS_FSL_DDRC_GEN1
-               Freescale DDR1 controller.
-
-               CONFIG_SYS_FSL_DDRC_GEN2
-               Freescale DDR2 controller.
-
-               CONFIG_SYS_FSL_DDRC_GEN3
-               Freescale DDR3 controller.
-
-               CONFIG_SYS_FSL_DDRC_GEN4
-               Freescale DDR4 controller.
-
-               CONFIG_SYS_FSL_DDRC_ARM_GEN3
-               Freescale DDR3 controller for ARM-based SoCs.
-
-               CONFIG_SYS_FSL_DDR1
-               Board config to use DDR1. It can be enabled for SoCs with
-               Freescale DDR1 or DDR2 controllers, depending on the board
-               implemetation.
-
-               CONFIG_SYS_FSL_DDR2
-               Board config to use DDR2. It can be enabled for SoCs with
-               Freescale DDR2 or DDR3 controllers, depending on the board
-               implementation.
-
-               CONFIG_SYS_FSL_DDR3
-               Board config to use DDR3. It can be enabled for SoCs with
-               Freescale DDR3 or DDR3L controllers.
-
-               CONFIG_SYS_FSL_DDR3L
-               Board config to use DDR3L. It can be enabled for SoCs with
-               DDR3L controllers.
-
                CONFIG_SYS_FSL_IFC_CLK_DIV
                Defines divider of platform clock(clock input to IFC controller).
 
                CONFIG_SYS_FSL_LBC_CLK_DIV
                Defines divider of platform clock(clock input to eLBC controller).
 
-               CONFIG_SYS_FSL_DDR_BE
-               Defines the DDR controller register space as Big Endian
-
-               CONFIG_SYS_FSL_DDR_LE
-               Defines the DDR controller register space as Little Endian
-
                CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
                Physical address from the view of DDR controllers. It is the
                same as CONFIG_SYS_DDR_SDRAM_BASE for  all Power SoCs. But
                it could be different for ARM SoCs.
 
-               CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
-               Number of controllers used as main memory.
-
-               CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
-               Number of controllers used for other than main memory.
-
-               CONFIG_SYS_FSL_SEC_BE
-               Defines the SEC controller register space as Big Endian
-
-               CONFIG_SYS_FSL_SEC_LE
-               Defines the SEC controller register space as Little Endian
-
 - MIPS CPU options:
                CONFIG_XWAY_SWAP_BYTES
 

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 1f86070b8a2c2343050974bd425d74cb4056722f..91a5863c97fb06f3849887e448a2bc2af7d0b0e6 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -193,6 +193,7 @@ config ARCH_LS2080A
        select FSL_IFC
        select FSL_LAYERSCAPE
        select FSL_LSCH3
+       select SYS_FSL_OTHER_DDR_NUM_CTRLS
        select GICV3
        select SKIP_LOWLEVEL_INIT
        select SYS_FSL_SRDS_1

diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig
index afb4e48e7e85032213178f01321377878b00bf29..034f15760b43478773325c13113a1e3410814ab8 100644 (file)
--- a/configs/ls2080aqds_SECURE_BOOT_defconfig
+++ b/configs/ls2080aqds_SECURE_BOOT_defconfig
@@ -54,6 +54,7 @@ CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y

diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig
index 15dadeb4e42027aaaff0bb4aeea2f7af53d912cf..d8efe46f3c6c041f863cf3e541207b082d6dfa42 100644 (file)
--- a/configs/ls2080aqds_defconfig
+++ b/configs/ls2080aqds_defconfig
@@ -57,6 +57,7 @@ CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y

diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index 9fc1801c15da01e420e69afb79df302b9a39e7e9..a0fbb7d3c347d640c4159ae9a10055c2d33fb715 100644 (file)
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -77,6 +77,7 @@ CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y

diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig
index d2dd95ea792d327165395b419c57bbe9b3a81172..9925333678b115f0eae07457574c9e815ca75752 100644 (file)
--- a/configs/ls2080aqds_qspi_defconfig
+++ b/configs/ls2080aqds_qspi_defconfig
@@ -58,6 +58,7 @@ CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y

diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig
index e2e4cfdd936480482723e2fbf3e1052dc18dc481..9d852531092d248325a67183bfcab9acd4568383 100644 (file)
--- a/configs/ls2080aqds_sdcard_defconfig
+++ b/configs/ls2080aqds_sdcard_defconfig
@@ -72,6 +72,7 @@ CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y

diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig
index 5378876f11b9a319c958a907a36a4d0f18d428c3..46dde0b6b8b40067b0d17daa1d7d0f3d775984e1 100644 (file)
--- a/configs/ls2080ardb_SECURE_BOOT_defconfig
+++ b/configs/ls2080ardb_SECURE_BOOT_defconfig
@@ -58,6 +58,7 @@ CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y

diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig
index 6570a466e0c5670a55eb737c2e9fe156972057de..87129967f258b9ddf0a1302926b78ea76d9fcf86 100644 (file)
--- a/configs/ls2080ardb_defconfig
+++ b/configs/ls2080ardb_defconfig
@@ -61,6 +61,7 @@ CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y

diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index 7c87f890c2c2f145c2daedebf90fcb6a2c7952a9..da463ebf42b49fa924664edb5ca9a4331bc1eb18 100644 (file)
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -81,6 +81,7 @@ CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y

diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig
index a426d6d48fb148f6509ae51e76052c9d46ab7f51..cc4bbaca436b45c21b6991708b430f6027cece22 100644 (file)
--- a/configs/ls2081ardb_defconfig
+++ b/configs/ls2081ardb_defconfig
@@ -59,6 +59,7 @@ CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y

diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig
index f082fa52bcc5f6df7c063a39caa5f59d50a81a97..c5cc05bd3a491c45476fb02d8043c88cd9f6aa3a 100644 (file)
--- a/configs/ls2088aqds_tfa_defconfig
+++ b/configs/ls2088aqds_tfa_defconfig
@@ -64,6 +64,7 @@ CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y

diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
index 1972fc908f54536d049cdadb61af14bccc58d0a3..008ee1f023d949d0a201d03c07214bd07ecfaa9f 100644 (file)
--- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
@@ -54,6 +54,7 @@ CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y

diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig
index dedc191edc0657e8e98653bb245654aae2b24ad5..bcf869ff12749e0a0966c821c5ddc1f566d88f22 100644 (file)
--- a/configs/ls2088ardb_qspi_defconfig
+++ b/configs/ls2088ardb_qspi_defconfig
@@ -61,6 +61,7 @@ CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y

diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
index 1674a2ce0916904ccc016dc88a5e848af7a0968e..f633af34bb05e6ba24cd3b66a89bf0d83e78d944 100644 (file)
--- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
@@ -59,6 +59,7 @@ CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y

diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig
index 071db6b1d2e4814444d3217b5a7393e425d43c49..3d8e201db1ab9f666fe751cf3d814898576470ac 100644 (file)
--- a/configs/ls2088ardb_tfa_defconfig
+++ b/configs/ls2088ardb_tfa_defconfig
@@ -66,6 +66,7 @@ CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y

diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index 22400a9b8bab5d9db05a5a99d4b13349dc0b8c5e..7f8f3570dd8c1972626c9c8dffb724a41705a4a9 100644 (file)
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -40,6 +40,9 @@ config FSL_DDR_SYNC_REFRESH
 config FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
        bool
 
+config SYS_FSL_OTHER_DDR_NUM_CTRLS
+       bool
+
 menu "Freescale DDR controllers"
        depends on SYS_FSL_DDR
 
@@ -63,6 +66,10 @@ config DIMM_SLOTS_PER_CTLR
        int "Number of DIMM slots per controller"
        default 1
 
+config SYS_FSL_DDR_MAIN_NUM_CTRLS
+       int "Number of controllers used as main memory"
+       default SYS_NUM_DDR_CTLRS
+
 config SYS_FSL_DDR_VER
        int
        default 50 if SYS_FSL_DDR_VER_50

diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h
index 2373abf3e31d5951ddc269a327c8c721c23ff40c..38063ba4842d072144efcbbce5e0b58f57847046 100644 (file)
--- a/include/configs/kontron_sl28.h
+++ b/include/configs/kontron_sl28.h
@@ -23,7 +23,6 @@
 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY      0
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_SYS_DDR_BLOCK2_BASE     0x2080000000ULL
-#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS      1
 
 /* early stack pointer */
 

diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h
index b104524becb1454e2483ec02d5f7e2c6510f1fee..8413e68f3a794bd82b43c978a07d41b02fb1227e 100644 (file)
--- a/include/configs/ls1028a_common.h
+++ b/include/configs/ls1028a_common.h
@@ -17,7 +17,6 @@
 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY      0
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_SYS_DDR_BLOCK2_BASE     0x2080000000ULL
-#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS      1
 
 /*
  * SMP Definitinos

diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
index 4b8462da7bcd7472b676e3000be7a305276f5ad0..21afe80e70de64085a2405042e9ceb74a7eed538 100644 (file)
--- a/include/configs/ls1088a_common.h
+++ b/include/configs/ls1088a_common.h
@@ -34,7 +34,6 @@
 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY      0
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_SYS_DDR_BLOCK2_BASE     0x8080000000ULL
-#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS      1
 /*
  * SMP Definitinos
  */

diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index ba5af6c34d344b0488c8d409353e32f8ac7610c8..e170b5aa2c70d07d9d3f710dce942bf1f4e2eb87 100644 (file)
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -21,15 +21,12 @@
 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY      0
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_SYS_DDR_BLOCK2_BASE     0x8080000000ULL
-#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS      2
 
 /*
  * SMP Definitinos
  */
 #define CPU_RELEASE_ADDR               secondary_boot_addr
 
-#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
-
 /*
  * This is not an accurate number. It is used in start.S. The frequency
  * will be udpated later when get_bus_freq(0) is available.

diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 61870717e8e18dcdce2ec553ca5d4516540c9cda..d39c0032c4a1c97fe5bd222104e5bcb9109cff86 100644 (file)
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -17,7 +17,6 @@
 #define CONFIG_SYS_DDR_SDRAM_BASE              0x80000000UL
 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY      0
 #define CONFIG_SYS_DDR_BLOCK2_BASE             0x2080000000ULL
-#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS      2
 #define CONFIG_SYS_SDRAM_SIZE                  0x200000000UL
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_MEM_INIT_VALUE          0xdeadbeef

diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h
index 025d7a1e74b61f81b8fa02146ab8f2a759f187e1..24229f6bc4482563dc9e27183b8580331c189adb 100644 (file)
--- a/include/fsl_ddr.h
+++ b/include/fsl_ddr.h
@@ -14,11 +14,6 @@
 
 struct cmd_tbl;
 
-#ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
-/* All controllers are for main memory */
-#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS      CONFIG_SYS_NUM_DDR_CTLRS
-#endif
-
 #ifdef CONFIG_SYS_FSL_DDR_LE
 #define ddr_in32(a)    in_le32(a)
 #define ddr_out32(a, v)        out_le32(a, v)