Add DDR3 detection timings for Rockchip RV1126 SoC.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
--- /dev/null
+{
+ {
+ {
+ .rank = 0x1,
+ .col = 0xC,
+ .bk = 0x3,
+ .bw = 0x0,
+ .dbw = 0x0,
+ .row_3_4 = 0x0,
+ .cs0_row = 0x10,
+ .cs1_row = 0x10,
+ .cs0_high16bit_row = 0x10,
+ .cs1_high16bit_row = 0x10,
+ .ddrconfig = 0
+ },
+ {
+ {0x351b1019},
+ {0x12030903},
+ {0x00000002},
+ {0x00001111},
+ {0x0000000c},
+ {0x00000000},
+ 0x000000ff
+ }
+ },
+ {
+ .ddr_freq = 1056, /* clock rate(MHz) */
+ .dramtype = DDR3,
+ .num_channels = 1,
+ .stride = 0,
+ .odt = 1
+ },
+ {
+ {
+ {0x00000000, 0x43042001}, /* MSTR */
+ {0x00000064, 0x008000b9}, /* RFSHTMG */
+ {0x000000d0, 0x00020103}, /* INIT0 */
+ {0x000000d4, 0x00690000}, /* INIT1 */
+ {0x000000d8, 0x00000100}, /* INIT2 */
+ {0x000000dc, 0x01240040}, /* INIT3 */
+ {0x000000e0, 0x00280000}, /* INIT4 */
+ {0x000000e4, 0x000c0000}, /* INIT5 */
+ {0x000000f4, 0x000f011f}, /* RANKCTL */
+ {0x00000100, 0x0f132414}, /* DRAMTMG0 */
+ {0x00000104, 0x000d0419}, /* DRAMTMG1 */
+ {0x00000108, 0x0507050b}, /* DRAMTMG2 */
+ {0x0000010c, 0x00202008}, /* DRAMTMG3 */
+ {0x00000110, 0x07020408}, /* DRAMTMG4 */
+ {0x00000114, 0x06060404}, /* DRAMTMG5 */
+ {0x00000120, 0x00000907}, /* DRAMTMG8 */
+ {0x00000180, 0x00a9002b}, /* ZQCTL0 */
+ {0x00000184, 0x00000000}, /* ZQCTL1 */
+ {0x00000190, 0x07050003}, /* DFITMG0 */
+ {0x00000198, 0x07000101}, /* DFILPCFG0 */
+ {0x000001a0, 0xc0400003}, /* DFIUPD0 */
+ {0x00000240, 0x06000610}, /* ODTCFG */
+ {0x00000244, 0x00000201}, /* ODTMAP */
+ {0x00000250, 0x00001f00}, /* SCHED */
+ {0x00000490, 0x00000001}, /* PCTRL_0 */
+ {0xffffffff, 0xffffffff}
+ }
+ },
+ {
+ {
+ {0x00000004, 0x0000008a}, /* PHYREG01 */
+ {0x00000014, 0x0000000e}, /* PHYREG05 */
+ {0x00000018, 0x00000000}, /* PHYREG06 */
+ {0x0000001c, 0x0000000a}, /* PHYREG07 */
+ {0xffffffff, 0xffffffff}
+ }
+ }
+},
--- /dev/null
+{
+ {
+ {
+ .rank = 0x1,
+ .col = 0xC,
+ .bk = 0x3,
+ .bw = 0x0,
+ .dbw = 0x0,
+ .row_3_4 = 0x0,
+ .cs0_row = 0x10,
+ .cs1_row = 0x10,
+ .cs0_high16bit_row = 0x10,
+ .cs1_high16bit_row = 0x10,
+ .ddrconfig = 0
+ },
+ {
+ {0x270a0509},
+ {0x08020401},
+ {0x00000002},
+ {0x00001111},
+ {0x0000000c},
+ {0x00000000},
+ 0x000000ff
+ }
+ },
+ {
+ .ddr_freq = 328, /* clock rate(MHz) */
+ .dramtype = DDR3,
+ .num_channels = 1,
+ .stride = 0,
+ .odt = 0
+ },
+ {
+ {
+ {0x00000000, 0x43042001}, /* MSTR */
+ {0x00000064, 0x0027003a}, /* RFSHTMG */
+ {0x000000d0, 0x00020052}, /* INIT0 */
+ {0x000000d4, 0x00220000}, /* INIT1 */
+ {0x000000d8, 0x00000100}, /* INIT2 */
+ {0x000000dc, 0x03100000}, /* INIT3 */
+ {0x000000e0, 0x00000000}, /* INIT4 */
+ {0x000000e4, 0x00090000}, /* INIT5 */
+ {0x000000f4, 0x000f011f}, /* RANKCTL */
+ {0x00000100, 0x07090b06}, /* DRAMTMG0 */
+ {0x00000104, 0x00050209}, /* DRAMTMG1 */
+ {0x00000108, 0x03030307}, /* DRAMTMG2 */
+ {0x0000010c, 0x00202006}, /* DRAMTMG3 */
+ {0x00000110, 0x03020203}, /* DRAMTMG4 */
+ {0x00000114, 0x03030202}, /* DRAMTMG5 */
+ {0x00000120, 0x00000903}, /* DRAMTMG8 */
+ {0x00000180, 0x00800020}, /* ZQCTL0 */
+ {0x00000184, 0x00000000}, /* ZQCTL1 */
+ {0x00000190, 0x07010001}, /* DFITMG0 */
+ {0x00000198, 0x07000101}, /* DFILPCFG0 */
+ {0x000001a0, 0xc0400003}, /* DFIUPD0 */
+ {0x00000240, 0x06000600}, /* ODTCFG */
+ {0x00000244, 0x00000201}, /* ODTMAP */
+ {0x00000250, 0x00001f00}, /* SCHED */
+ {0x00000490, 0x00000001}, /* PCTRL_0 */
+ {0xffffffff, 0xffffffff}
+ }
+ },
+ {
+ {
+ {0x00000004, 0x0000008a}, /* PHYREG01 */
+ {0x00000014, 0x00000005}, /* PHYREG05 */
+ {0x00000018, 0x00000000}, /* PHYREG06 */
+ {0x0000001c, 0x00000005}, /* PHYREG07 */
+ {0xffffffff, 0xffffffff}
+ }
+ }
+},
--- /dev/null
+{
+ {
+ {
+ .rank = 0x1,
+ .col = 0xC,
+ .bk = 0x3,
+ .bw = 0x0,
+ .dbw = 0x0,
+ .row_3_4 = 0x0,
+ .cs0_row = 0x10,
+ .cs1_row = 0x10,
+ .cs0_high16bit_row = 0x10,
+ .cs1_high16bit_row = 0x10,
+ .ddrconfig = 0
+ },
+ {
+ {0x290b060a},
+ {0x0a020401},
+ {0x00000002},
+ {0x00001111},
+ {0x0000000c},
+ {0x00000000},
+ 0x000000ff
+ }
+ },
+ {
+ .ddr_freq = 396, /* clock rate(MHz) */
+ .dramtype = DDR3,
+ .num_channels = 1,
+ .stride = 0,
+ .odt = 0
+ },
+ {
+ {
+ {0x00000000, 0x43042001}, /* MSTR */
+ {0x00000064, 0x00300046}, /* RFSHTMG */
+ {0x000000d0, 0x00020062}, /* INIT0 */
+ {0x000000d4, 0x00280000}, /* INIT1 */
+ {0x000000d8, 0x00000100}, /* INIT2 */
+ {0x000000dc, 0x05200000}, /* INIT3 */
+ {0x000000e0, 0x00000000}, /* INIT4 */
+ {0x000000e4, 0x00090000}, /* INIT5 */
+ {0x000000f4, 0x000f011f}, /* RANKCTL */
+ {0x00000100, 0x070a0d07}, /* DRAMTMG0 */
+ {0x00000104, 0x0005020b}, /* DRAMTMG1 */
+ {0x00000108, 0x03030407}, /* DRAMTMG2 */
+ {0x0000010c, 0x00202006}, /* DRAMTMG3 */
+ {0x00000110, 0x03020204}, /* DRAMTMG4 */
+ {0x00000114, 0x03030202}, /* DRAMTMG5 */
+ {0x00000120, 0x00000904}, /* DRAMTMG8 */
+ {0x00000180, 0x00800020}, /* ZQCTL0 */
+ {0x00000184, 0x00000000}, /* ZQCTL1 */
+ {0x00000190, 0x07010001}, /* DFITMG0 */
+ {0x00000198, 0x07000101}, /* DFILPCFG0 */
+ {0x000001a0, 0xc0400003}, /* DFIUPD0 */
+ {0x00000240, 0x06000604}, /* ODTCFG */
+ {0x00000244, 0x00000201}, /* ODTMAP */
+ {0x00000250, 0x00001f00}, /* SCHED */
+ {0x00000490, 0x00000001}, /* PCTRL_0 */
+ {0xffffffff, 0xffffffff}
+ }
+ },
+ {
+ {
+ {0x00000004, 0x0000008a}, /* PHYREG01 */
+ {0x00000014, 0x00000006}, /* PHYREG05 */
+ {0x00000018, 0x00000000}, /* PHYREG06 */
+ {0x0000001c, 0x00000005}, /* PHYREG07 */
+ {0xffffffff, 0xffffffff}
+ }
+ }
+},
--- /dev/null
+{
+ {
+ {
+ .rank = 0x1,
+ .col = 0xC,
+ .bk = 0x3,
+ .bw = 0x0,
+ .dbw = 0x0,
+ .row_3_4 = 0x0,
+ .cs0_row = 0x10,
+ .cs1_row = 0x10,
+ .cs0_high16bit_row = 0x10,
+ .cs1_high16bit_row = 0x10,
+ .ddrconfig = 0
+ },
+ {
+ {0x2c0f080e},
+ {0x0d030502},
+ {0x00000002},
+ {0x00001111},
+ {0x0000000c},
+ {0x00000000},
+ 0x000000ff
+ }
+ },
+ {
+ .ddr_freq = 528, /* clock rate(MHz) */
+ .dramtype = DDR3,
+ .num_channels = 1,
+ .stride = 0,
+ .odt = 0
+ },
+ {
+ {
+ {0x00000000, 0x43042001}, /* MSTR */
+ {0x00000064, 0x0040005d}, /* RFSHTMG */
+ {0x000000d0, 0x00020082}, /* INIT0 */
+ {0x000000d4, 0x00350000}, /* INIT1 */
+ {0x000000d8, 0x00000100}, /* INIT2 */
+ {0x000000dc, 0x09400000}, /* INIT3 */
+ {0x000000e0, 0x00080000}, /* INIT4 */
+ {0x000000e4, 0x00090000}, /* INIT5 */
+ {0x000000f4, 0x000f011f}, /* RANKCTL */
+ {0x00000100, 0x090e120a}, /* DRAMTMG0 */
+ {0x00000104, 0x0007020e}, /* DRAMTMG1 */
+ {0x00000108, 0x03040407}, /* DRAMTMG2 */
+ {0x0000010c, 0x00202006}, /* DRAMTMG3 */
+ {0x00000110, 0x04020305}, /* DRAMTMG4 */
+ {0x00000114, 0x03030302}, /* DRAMTMG5 */
+ {0x00000120, 0x00000904}, /* DRAMTMG8 */
+ {0x00000180, 0x00800020}, /* ZQCTL0 */
+ {0x00000184, 0x00000000}, /* ZQCTL1 */
+ {0x00000190, 0x07020001}, /* DFITMG0 */
+ {0x00000198, 0x07000101}, /* DFILPCFG0 */
+ {0x000001a0, 0xc0400003}, /* DFIUPD0 */
+ {0x00000240, 0x06000608}, /* ODTCFG */
+ {0x00000244, 0x00000201}, /* ODTMAP */
+ {0x00000250, 0x00001f00}, /* SCHED */
+ {0x00000490, 0x00000001}, /* PCTRL_0 */
+ {0xffffffff, 0xffffffff}
+ }
+ },
+ {
+ {
+ {0x00000004, 0x0000008a}, /* PHYREG01 */
+ {0x00000014, 0x00000008}, /* PHYREG05 */
+ {0x00000018, 0x00000000}, /* PHYREG06 */
+ {0x0000001c, 0x00000006}, /* PHYREG07 */
+ {0xffffffff, 0xffffffff}
+ }
+ }
+},
--- /dev/null
+{
+ {
+ {
+ .rank = 0x1,
+ .col = 0xC,
+ .bk = 0x3,
+ .bw = 0x0,
+ .dbw = 0x0,
+ .row_3_4 = 0x0,
+ .cs0_row = 0x10,
+ .cs1_row = 0x10,
+ .cs0_high16bit_row = 0x10,
+ .cs1_high16bit_row = 0x10,
+ .ddrconfig = 0
+ },
+ {
+ {0x2f120a11},
+ {0x0f020602},
+ {0x00000002},
+ {0x00001111},
+ {0x0000000c},
+ {0x00000000},
+ 0x000000ff
+ }
+ },
+ {
+ .ddr_freq = 664, /* clock rate(MHz) */
+ .dramtype = DDR3,
+ .num_channels = 1,
+ .stride = 0,
+ .odt = 1
+ },
+ {
+ {
+ {0x00000000, 0x43042001}, /* MSTR */
+ {0x00000064, 0x00500075}, /* RFSHTMG */
+ {0x000000d0, 0x000200a4}, /* INIT0 */
+ {0x000000d4, 0x00420000}, /* INIT1 */
+ {0x000000d8, 0x00000100}, /* INIT2 */
+ {0x000000dc, 0x0b600040}, /* INIT3 */
+ {0x000000e0, 0x00100000}, /* INIT4 */
+ {0x000000e4, 0x00090000}, /* INIT5 */
+ {0x000000f4, 0x000f011f}, /* RANKCTL */
+ {0x00000100, 0x0a0f160c}, /* DRAMTMG0 */
+ {0x00000104, 0x00080211}, /* DRAMTMG1 */
+ {0x00000108, 0x04050508}, /* DRAMTMG2 */
+ {0x0000010c, 0x00202006}, /* DRAMTMG3 */
+ {0x00000110, 0x05020306}, /* DRAMTMG4 */
+ {0x00000114, 0x04040302}, /* DRAMTMG5 */
+ {0x00000120, 0x00000905}, /* DRAMTMG8 */
+ {0x00000180, 0x00800020}, /* ZQCTL0 */
+ {0x00000184, 0x00000000}, /* ZQCTL1 */
+ {0x00000190, 0x07030002}, /* DFITMG0 */
+ {0x00000198, 0x07000101}, /* DFILPCFG0 */
+ {0x000001a0, 0xc0400003}, /* DFIUPD0 */
+ {0x00000240, 0x0600060c}, /* ODTCFG */
+ {0x00000244, 0x00000201}, /* ODTMAP */
+ {0x00000250, 0x00001f00}, /* SCHED */
+ {0x00000490, 0x00000001}, /* PCTRL_0 */
+ {0xffffffff, 0xffffffff}
+ }
+ },
+ {
+ {
+ {0x00000004, 0x0000008a}, /* PHYREG01 */
+ {0x00000014, 0x0000000a}, /* PHYREG05 */
+ {0x00000018, 0x00000000}, /* PHYREG06 */
+ {0x0000001c, 0x00000007}, /* PHYREG07 */
+ {0xffffffff, 0xffffffff}
+ }
+ }
+},
--- /dev/null
+{
+ {
+ {
+ .rank = 0x1,
+ .col = 0xC,
+ .bk = 0x3,
+ .bw = 0x0,
+ .dbw = 0x0,
+ .row_3_4 = 0x0,
+ .cs0_row = 0x10,
+ .cs1_row = 0x10,
+ .cs0_high16bit_row = 0x10,
+ .cs1_high16bit_row = 0x10,
+ .ddrconfig = 0
+ },
+ {
+ {0x30150c13},
+ {0x10030702},
+ {0x00000002},
+ {0x00001111},
+ {0x0000000c},
+ {0x00000000},
+ 0x000000ff
+ }
+ },
+ {
+ .ddr_freq = 784, /* clock rate(MHz) */
+ .dramtype = DDR3,
+ .num_channels = 1,
+ .stride = 0,
+ .odt = 1
+ },
+ {
+ {
+ {0x00000000, 0x43042001}, /* MSTR */
+ {0x00000064, 0x005f008a}, /* RFSHTMG */
+ {0x000000d0, 0x000200c1}, /* INIT0 */
+ {0x000000d4, 0x004e0000}, /* INIT1 */
+ {0x000000d8, 0x00000100}, /* INIT2 */
+ {0x000000dc, 0x0d700040}, /* INIT3 */
+ {0x000000e0, 0x00180000}, /* INIT4 */
+ {0x000000e4, 0x00090000}, /* INIT5 */
+ {0x000000f4, 0x000f011f}, /* RANKCTL */
+ {0x00000100, 0x0c101a0f}, /* DRAMTMG0 */
+ {0x00000104, 0x000a0314}, /* DRAMTMG1 */
+ {0x00000108, 0x04060509}, /* DRAMTMG2 */
+ {0x0000010c, 0x00202006}, /* DRAMTMG3 */
+ {0x00000110, 0x06020306}, /* DRAMTMG4 */
+ {0x00000114, 0x04040303}, /* DRAMTMG5 */
+ {0x00000120, 0x00000906}, /* DRAMTMG8 */
+ {0x00000180, 0x00800020}, /* ZQCTL0 */
+ {0x00000184, 0x00000000}, /* ZQCTL1 */
+ {0x00000190, 0x07040002}, /* DFITMG0 */
+ {0x00000198, 0x07000101}, /* DFILPCFG0 */
+ {0x000001a0, 0xc0400003}, /* DFIUPD0 */
+ {0x00000240, 0x0600060c}, /* ODTCFG */
+ {0x00000244, 0x00000201}, /* ODTMAP */
+ {0x00000250, 0x00001f00}, /* SCHED */
+ {0x00000490, 0x00000001}, /* PCTRL_0 */
+ {0xffffffff, 0xffffffff}
+ }
+ },
+ {
+ {
+ {0x00000004, 0x0000008a}, /* PHYREG01 */
+ {0x00000014, 0x0000000b}, /* PHYREG05 */
+ {0x00000018, 0x00000000}, /* PHYREG06 */
+ {0x0000001c, 0x00000008}, /* PHYREG07 */
+ {0xffffffff, 0xffffffff}
+ }
+ }
+},
--- /dev/null
+{
+ {
+ {
+ .rank = 0x1,
+ .col = 0xC,
+ .bk = 0x3,
+ .bw = 0x0,
+ .dbw = 0x0,
+ .row_3_4 = 0x0,
+ .cs0_row = 0x10,
+ .cs1_row = 0x10,
+ .cs0_high16bit_row = 0x10,
+ .cs1_high16bit_row = 0x10,
+ .ddrconfig = 0
+ },
+ {
+ {0x33180e16},
+ {0x10030803},
+ {0x00000002},
+ {0x00001111},
+ {0x0000000c},
+ {0x00000000},
+ 0x000000ff
+ }
+ },
+ {
+ .ddr_freq = 924, /* clock rate(MHz) */
+ .dramtype = DDR3,
+ .num_channels = 1,
+ .stride = 0,
+ .odt = 1
+ },
+ {
+ {
+ {0x00000000, 0x43042001}, /* MSTR */
+ {0x00000064, 0x007000a2}, /* RFSHTMG */
+ {0x000000d0, 0x000200e3}, /* INIT0 */
+ {0x000000d4, 0x005c0000}, /* INIT1 */
+ {0x000000d8, 0x00000100}, /* INIT2 */
+ {0x000000dc, 0x0f140040}, /* INIT3 */
+ {0x000000e0, 0x00200000}, /* INIT4 */
+ {0x000000e4, 0x000b0000}, /* INIT5 */
+ {0x000000f4, 0x000f011f}, /* RANKCTL */
+ {0x00000100, 0x0d111f11}, /* DRAMTMG0 */
+ {0x00000104, 0x000c0317}, /* DRAMTMG1 */
+ {0x00000108, 0x0507050a}, /* DRAMTMG2 */
+ {0x0000010c, 0x00202007}, /* DRAMTMG3 */
+ {0x00000110, 0x07020307}, /* DRAMTMG4 */
+ {0x00000114, 0x05050403}, /* DRAMTMG5 */
+ {0x00000120, 0x00000907}, /* DRAMTMG8 */
+ {0x00000180, 0x00940025}, /* ZQCTL0 */
+ {0x00000184, 0x00000000}, /* ZQCTL1 */
+ {0x00000190, 0x07050003}, /* DFITMG0 */
+ {0x00000198, 0x07000101}, /* DFILPCFG0 */
+ {0x000001a0, 0xc0400003}, /* DFIUPD0 */
+ {0x00000240, 0x06000610}, /* ODTCFG */
+ {0x00000244, 0x00000201}, /* ODTMAP */
+ {0x00000250, 0x00001f00}, /* SCHED */
+ {0x00000490, 0x00000001}, /* PCTRL_0 */
+ {0xffffffff, 0xffffffff}
+ }
+ },
+ {
+ {
+ {0x00000004, 0x0000008a}, /* PHYREG01 */
+ {0x00000014, 0x0000000d}, /* PHYREG05 */
+ {0x00000018, 0x00000000}, /* PHYREG06 */
+ {0x0000001c, 0x00000009}, /* PHYREG07 */
+ {0xffffffff, 0xffffffff}
+ }
+ }
+},
projects / u-boot.git / commitdiff
