ARM: dts: socfpga: Add u-boot,dm-pre-reloc to necessary clock nodes

Add the pre-reloc DT markers to clock nodes needed in SPL and early
U-Boot stages. This is required to let the Arria10 clock driver start
early and provide clock information for UART and SDMMC.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>

diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
index 05425a03fc141e874eab2bbac1d2de171189cc43..ce000512efbedcc36925109c56d92c22f7992c2a 100644 (file)
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -94,29 +94,35 @@
                clkmgr@ffd04000 {
                                compatible = "altr,clk-mgr";
                                reg = <0xffd04000 0x1000>;
+                               u-boot,dm-pre-reloc;
 
                                clocks {
                                        #address-cells = <1>;
                                        #size-cells = <0>;
+                                       u-boot,dm-pre-reloc;
 
                                        cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
                                                #clock-cells = <0>;
                                                compatible = "fixed-clock";
+                                               u-boot,dm-pre-reloc;
                                        };
 
                                        cb_intosc_ls_clk: cb_intosc_ls_clk {
                                                #clock-cells = <0>;
                                                compatible = "fixed-clock";
+                                               u-boot,dm-pre-reloc;
                                        };
 
                                        f2s_free_clk: f2s_free_clk {
                                                #clock-cells = <0>;
                                                compatible = "fixed-clock";
+                                               u-boot,dm-pre-reloc;
                                        };
 
                                        osc1: osc1 {
                                                #clock-cells = <0>;
                                                compatible = "fixed-clock";
+                                               u-boot,dm-pre-reloc;
                                        };
 
                                        main_pll: main_pll@40 {
@@ -127,6 +133,7 @@
                                                clocks = <&osc1>, <&cb_intosc_ls_clk>,
                                                         <&f2s_free_clk>;
                                                reg = <0x40>;
+                                               u-boot,dm-pre-reloc;
 
                                                main_mpu_base_clk: main_mpu_base_clk {
                                                        #clock-cells = <0>;
@@ -215,6 +222,7 @@
                                                clocks = <&osc1>, <&cb_intosc_ls_clk>,
                                                         <&f2s_free_clk>, <&main_periph_ref_clk>;
                                                reg = <0xC0>;
+                                               u-boot,dm-pre-reloc;
 
                                                peri_mpu_base_clk: peri_mpu_base_clk {
                                                        #clock-cells = <0>;

diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi
index 4018a5b929603b89fb948149c963d8dd72f759e3..9160c20bd0b61f5b0754fd54ce734f1ace4a4b32 100644 (file)
--- a/arch/arm/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi
@@ -167,3 +167,28 @@
 &watchdog1 {
        status = "okay";
 };
+
+/* Clock available early */
+&main_noc_base_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&main_periph_ref_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&peri_noc_base_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&noc_free_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&l4_mp_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&l4_sp_clk {
+       u-boot,dm-pre-reloc;
+};

diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
index 9c6070ded915ffe6d15e170e10fcd07953dc980e..998d8112101401b95dabc5d476138bdcba2d4708 100644 (file)
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
@@ -38,3 +38,20 @@
                             <48 IRQ_TYPE_LEVEL_HIGH>;
        };
 };
+
+/* Clock available early */
+&main_sdmmc_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&peri_sdmmc_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&sdmmc_free_clk {
+       u-boot,dm-pre-reloc;
+};
+
+&sdmmc_clk {
+       u-boot,dm-pre-reloc;
+};