global: Migrate CONFIG_HPS* symbols to the CFG namespace

Migrate all of CONFIG_HPS* to the CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/mach-socfpga/qts-filter.sh b/arch/arm/mach-socfpga/qts-filter.sh
index a49cd1b68a9e7ba1d586bf04e9796b6989527483..6416252d4ed81913280058f85bc0cdcdab584e30 100755 (executable)
--- a/arch/arm/mach-socfpga/qts-filter.sh
+++ b/arch/arm/mach-socfpga/qts-filter.sh
@@ -36,7 +36,7 @@ EOF
        # Retrieve the scan chain lengths
        fix_newlines_in_macros \
                ${in_bsp_dir}/generated/iocsr_config_${soc}.h |
-       grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' | tr -d "()"
+       grep 'CFG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH'    | tr -d "()"
 
        echo ""
 
@@ -115,7 +115,7 @@ EOF
        # Retrieve the pll config and zap parenthesis
        fix_newlines_in_macros \
                ${in_bsp_dir}/generated/pll_config.h |
-       sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}'
+       sed -n '/CFG_HPS/ !b; :next {/CFG_HPS/ s/[()]//g;/endif/ b;p;n;b next}'
 
        cat << EOF
 
@@ -128,7 +128,7 @@ EOF
 # Filter out only the macros which are actually used by the code
 #
 grep_sdram_config() {
-       egrep "#define (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_ACTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_EMR_OCD_ENABLE|RW_MGR_EMR|RW_MGR_EMR2|RW_MGR_EMR3|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_INIT_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MR_CALIB|RW_MGR_MR_USER|RW_MGR_MR_DLL_RESET|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_NOP|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_REFRESH|RW_MGR_REFRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|AFI_CLK_FREQ|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP)[[:space:]]"
+       egrep "#define (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CFG_HPS_SDR_CTRLCFG_DRAMODT_READ|CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP|CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN|CFG_HPS_SDR_CTRLCFG_FPGAPORTRST|CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_ACTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_EMR_OCD_ENABLE|RW_MGR_EMR|RW_MGR_EMR2|RW_MGR_EMR3|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_INIT_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MR_CALIB|RW_MGR_MR_USER|RW_MGR_MR_DLL_RESET|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_NOP|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_REFRESH|RW_MGR_REFRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|AFI_CLK_FREQ|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL|CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR|CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC|CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP)[[:space:]]"
 }
 
 #
@@ -161,7 +161,7 @@ EOF
        fix_newlines_in_macros \
                ${in_bsp_dir}/generated/sdram/sdram_config.h |
        sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" |
-       sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' |
+       sed -n '/CFG_HPS/ !b; :next {/CFG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' |
                sort -u | grep_sdram_config
 
        echo ""

diff --git a/arch/arm/mach-socfpga/wrap_iocsr_config.c b/arch/arm/mach-socfpga/wrap_iocsr_config.c
index f810fade92a907dd41de01715dccf6f81498ddf8..ce86f04cad1f5a9a82815ca06df2f9b717338c58 100644 (file)
--- a/arch/arm/mach-socfpga/wrap_iocsr_config.c
+++ b/arch/arm/mach-socfpga/wrap_iocsr_config.c
@@ -17,19 +17,19 @@ int iocsr_get_config_table(const unsigned int chain_id,
        switch (chain_id) {
        case 0:
                *table = iocsr_scan_chain0_table;
-               *table_len = CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH;
+               *table_len = CFG_HPS_IOCSR_SCANCHAIN0_LENGTH;
                break;
        case 1:
                *table = iocsr_scan_chain1_table;
-               *table_len = CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH;
+               *table_len = CFG_HPS_IOCSR_SCANCHAIN1_LENGTH;
                break;
        case 2:
                *table = iocsr_scan_chain2_table;
-               *table_len = CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH;
+               *table_len = CFG_HPS_IOCSR_SCANCHAIN2_LENGTH;
                break;
        case 3:
                *table = iocsr_scan_chain3_table;
-               *table_len = CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH;
+               *table_len = CFG_HPS_IOCSR_SCANCHAIN3_LENGTH;
                break;
        default:
                return -EINVAL;

diff --git a/arch/arm/mach-socfpga/wrap_pll_config.c b/arch/arm/mach-socfpga/wrap_pll_config.c
index bd631e0fb5fbf9de47cd4aaf0ad288b27dcd7803..0c40ae987613ac30af29e3b491e0349b6cefdc32 100644 (file)
--- a/arch/arm/mach-socfpga/wrap_pll_config.c
+++ b/arch/arm/mach-socfpga/wrap_pll_config.c
@@ -8,116 +8,116 @@
 #include <qts/pll_config.h>
 
 #define MAIN_VCO_BASE (                                        \
-       (CONFIG_HPS_MAINPLLGRP_VCO_DENOM <<             \
+       (CFG_HPS_MAINPLLGRP_VCO_DENOM <<                \
                CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) |   \
-       (CONFIG_HPS_MAINPLLGRP_VCO_NUMER <<             \
+       (CFG_HPS_MAINPLLGRP_VCO_NUMER <<                \
                CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET)     \
        )
 
 #define PERI_VCO_BASE (                                        \
-       (CONFIG_HPS_PERPLLGRP_VCO_PSRC <<               \
+       (CFG_HPS_PERPLLGRP_VCO_PSRC <<          \
                CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) |     \
-       (CONFIG_HPS_PERPLLGRP_VCO_DENOM <<              \
+       (CFG_HPS_PERPLLGRP_VCO_DENOM <<         \
                CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) |    \
-       (CONFIG_HPS_PERPLLGRP_VCO_NUMER <<              \
+       (CFG_HPS_PERPLLGRP_VCO_NUMER <<         \
                CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET)      \
        )
 
 #define SDR_VCO_BASE (                                 \
-       (CONFIG_HPS_SDRPLLGRP_VCO_SSRC <<               \
+       (CFG_HPS_SDRPLLGRP_VCO_SSRC <<          \
                CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) |     \
-       (CONFIG_HPS_SDRPLLGRP_VCO_DENOM <<              \
+       (CFG_HPS_SDRPLLGRP_VCO_DENOM <<         \
                CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) |    \
-       (CONFIG_HPS_SDRPLLGRP_VCO_NUMER <<              \
+       (CFG_HPS_SDRPLLGRP_VCO_NUMER <<         \
                CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET)      \
        )
 
 static const struct cm_config cm_default_cfg = {
        /* main group */
        MAIN_VCO_BASE,
-       (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
+       (CFG_HPS_MAINPLLGRP_MPUCLK_CNT <<
                CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
-       (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
+       (CFG_HPS_MAINPLLGRP_MAINCLK_CNT <<
                CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
-       (CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
+       (CFG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
                CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
-       (CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
+       (CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
                CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
-       (CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
+       (CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
                CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
-       (CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
+       (CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
                CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
-       (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
+       (CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
                CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
-       (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
+       (CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
                CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
-       (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
+       (CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
                CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
-       (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
+       (CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
                CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
-       (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
+       (CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
                CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
-       (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
+       (CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
                CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
-       (CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
+       (CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
                CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
-       (CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
+       (CFG_HPS_MAINPLLGRP_L4SRC_L4MP <<
                CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
-       (CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
+       (CFG_HPS_MAINPLLGRP_L4SRC_L4SP <<
                CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
 
        /* peripheral group */
        PERI_VCO_BASE,
-       (CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
+       (CFG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
                CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
-       (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
+       (CFG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
                CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
-       (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
+       (CFG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
                CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
-       (CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
+       (CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
                CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
-       (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
+       (CFG_HPS_PERPLLGRP_PERBASECLK_CNT <<
                CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
-       (CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
+       (CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
                CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
-       (CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
+       (CFG_HPS_PERPLLGRP_DIV_USBCLK <<
                CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
-       (CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
+       (CFG_HPS_PERPLLGRP_DIV_SPIMCLK <<
                CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
-       (CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
+       (CFG_HPS_PERPLLGRP_DIV_CAN0CLK <<
                CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
-       (CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
+       (CFG_HPS_PERPLLGRP_DIV_CAN1CLK <<
                CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
-       (CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
+       (CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
                CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
-       (CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
+       (CFG_HPS_PERPLLGRP_SRC_QSPI <<
                CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
-       (CONFIG_HPS_PERPLLGRP_SRC_NAND <<
+       (CFG_HPS_PERPLLGRP_SRC_NAND <<
                CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
-       (CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
+       (CFG_HPS_PERPLLGRP_SRC_SDMMC <<
                CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
 
        /* sdram pll group */
        SDR_VCO_BASE,
-       (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
+       (CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
                CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
-       (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
+       (CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
                CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
-       (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
+       (CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
                CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
-       (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
+       (CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
                CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
-       (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
+       (CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
                CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
-       (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
+       (CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
                CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
-       (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
+       (CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
                CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
-       (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
+       (CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
                CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
 
        /* altera group */
-       CONFIG_HPS_ALTERAGRP_MPUCLK,
+       CFG_HPS_ALTERAGRP_MPUCLK,
 };
 
 const struct cm_config * const cm_get_default_config(void)
@@ -128,19 +128,19 @@ const struct cm_config * const cm_get_default_config(void)
 const unsigned int cm_get_osc_clk_hz(const int osc)
 {
        if (osc == 1)
-               return CONFIG_HPS_CLK_OSC1_HZ;
+               return CFG_HPS_CLK_OSC1_HZ;
        else if (osc == 2)
-               return CONFIG_HPS_CLK_OSC2_HZ;
+               return CFG_HPS_CLK_OSC2_HZ;
        else
                return 0;
 }
 
 const unsigned int cm_get_f2s_per_ref_clk_hz(void)
 {
-       return CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+       return CFG_HPS_CLK_F2S_PER_REF_HZ;
 }
 
 const unsigned int cm_get_f2s_sdr_ref_clk_hz(void)
 {
-       return CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
+       return CFG_HPS_CLK_F2S_SDR_REF_HZ;
 }

diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c b/arch/arm/mach-socfpga/wrap_sdram_config.c
index 4ea32e72c7c9e2cb1cae4593980fbf5face57584..cd3a0f6633556c61384cffc1672999e983f2e122 100644 (file)
--- a/arch/arm/mach-socfpga/wrap_sdram_config.c
+++ b/arch/arm/mach-socfpga/wrap_sdram_config.c
@@ -12,180 +12,180 @@
 
 static const struct socfpga_sdram_config sdram_config = {
        .ctrl_cfg =
-               (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
+               (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
                        SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB)                |
-               (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
+               (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
                        SDR_CTRLGRP_CTRLCFG_MEMBL_LSB)                  |
-               (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
+               (CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
                        SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB)              |
-               (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
+               (CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
                        SDR_CTRLGRP_CTRLCFG_ECCEN_LSB)                  |
-               (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
+               (CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
                        SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB)              |
-               (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
+               (CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
                        SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB)              |
-               (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
+               (CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
                        SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB)            |
-               (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
+               (CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
                        SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB)               |
-               (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
+               (CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
                        SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
        .dram_timing1 =
-               (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
+               (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
                        SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB)               |
-               (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
+               (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
                        SDR_CTRLGRP_DRAMTIMING1_TAL_LSB)                |
-               (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
+               (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
                        SDR_CTRLGRP_DRAMTIMING1_TCL_LSB)                |
-               (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
+               (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
                        SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB)               |
-               (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
+               (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
                        SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB)               |
-               (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
+               (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
                        SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
        .dram_timing2 =
-               (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
+               (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
                        SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB)              |
-               (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
+               (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
                        SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB)               |
-               (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
+               (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
                        SDR_CTRLGRP_DRAMTIMING2_TRP_LSB)                |
-               (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
+               (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
                        SDR_CTRLGRP_DRAMTIMING2_TWR_LSB)                |
-               (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
+               (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
                        SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
        .dram_timing3 =
-               (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
+               (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
                        SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB)               |
-               (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
+               (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
                        SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB)               |
-               (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
+               (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
                        SDR_CTRLGRP_DRAMTIMING3_TRC_LSB)                |
-               (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
+               (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
                        SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB)               |
-               (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
+               (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
                        SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
        .dram_timing4 =
-               (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
+               (CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
                        SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB)       |
-               (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
+               (CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
                        SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
        .lowpwr_timing =
-               (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
+               (CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
                        SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB)      |
-               (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
+               (CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
                        SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
        .dram_odt =
-               (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
+               (CFG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
                        SDR_CTRLGRP_DRAMODT_READ_LSB)                   |
-               (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
+               (CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
                        SDR_CTRLGRP_DRAMODT_WRITE_LSB),
-#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2)      /* DDR3 */
+#if (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */
        .extratime1 =
-               (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
+               (CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
                                SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB)            |
-               (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
+               (CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
                                SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB)         |
-               (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
+               (CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
                                SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
 #endif
        .dram_addrw =
-               (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
+               (CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
                        SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB)              |
-               (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
+               (CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
                        SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB)              |
-               (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
+               (CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
                        SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB)             |
-               ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
+               ((CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
                        SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
        .dram_if_width =
-               (CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
+               (CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
                        SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
        .dram_dev_width =
-               (CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
+               (CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
                        SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
        .dram_intr =
-               (CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
+               (CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
                        SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
        .lowpwr_eq =
-               (CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
+               (CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
                        SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
        .static_cfg =
-               (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
+               (CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
                        SDR_CTRLGRP_STATICCFG_MEMBL_LSB)                |
-               (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
+               (CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
                        SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
        .ctrl_width =
-               (CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
+               (CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
                        SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
        .cport_width =
-               (CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
+               (CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
                        SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
        .cport_wmap =
-               (CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
+               (CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
                        SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
        .cport_rmap =
-               (CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
+               (CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
                        SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
        .rfifo_cmap =
-               (CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
+               (CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
                        SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
        .wfifo_cmap =
-               (CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
+               (CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
                        SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
        .cport_rdwr =
-               (CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
+               (CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
                        SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
        .port_cfg =
-               (CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
+               (CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
                        SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
-       .fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
+       .fpgaport_rst = CFG_HPS_SDR_CTRLCFG_FPGAPORTRST,
        .fifo_cfg =
-               (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
+               (CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
                        SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB)               |
-               (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
+               (CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
                        SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
        .mp_priority =
-               (CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
+               (CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
                        SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
        .mp_weight0 =
-               (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
+               (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
                        SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
        .mp_weight1 =
-               (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
+               (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
                        SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
-               (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
+               (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
                        SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
        .mp_weight2 =
-               (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
+               (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
                        SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
        .mp_weight3 =
-               (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
+               (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
                        SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
        .mp_pacing0 =
-               (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
+               (CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
                        SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
        .mp_pacing1 =
-               (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
+               (CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
                        SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
-               (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
+               (CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
                        SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
        .mp_pacing2 =
-               (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
+               (CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
                        SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
        .mp_pacing3 =
-               (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
+               (CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
                        SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
        .mp_threshold0 =
-               (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
+               (CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
                        SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
        .mp_threshold1 =
-               (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
+               (CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
                        SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
        .mp_threshold2 =
-               (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
+               (CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
                        SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
-       .phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
+       .phy_ctrl0 = CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
 };
 
 static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
@@ -202,7 +202,7 @@ static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
        .guaranteed_write_wait3         = RW_MGR_GUARANTEED_WRITE_WAIT3,
        .idle_loop1                     = RW_MGR_IDLE_LOOP1,
        .idle_loop2                     = RW_MGR_IDLE_LOOP2,
-#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1)      /* DDR2 */
+#if (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */
        .emr                            = RW_MGR_EMR,
        .emr2                           = RW_MGR_EMR2,
        .emr3                           = RW_MGR_EMR3,
@@ -213,7 +213,7 @@ static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
        .mr_user                        = RW_MGR_MR_USER,
        .mr_dll_reset                   = RW_MGR_MR_DLL_RESET,
        .emr_ocd_enable                 = RW_MGR_EMR_OCD_ENABLE,
-#elif (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2)    /* DDR3 */
+#elif (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2)       /* DDR3 */
        .activate_1                     = RW_MGR_ACTIVATE_1,
        .idle                           = RW_MGR_IDLE,
        .init_reset_0_cke_0             = RW_MGR_INIT_RESET_0_CKE_0,
@@ -287,7 +287,7 @@ static const struct socfpga_sdram_io_config io_config = {
 };
 
 static const struct socfpga_sdram_misc_config misc_config = {
-#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1)      /* DDR2 */
+#if (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */
        .afi_clk_freq                   = AFI_CLK_FREQ,
 #endif
        .afi_rate_ratio                 = AFI_RATE_RATIO,

diff --git a/board/altera/arria5-socdk/qts/iocsr_config.h b/board/altera/arria5-socdk/qts/iocsr_config.h
index 69a92de6361b79632bce84c08daabe2cd75c68a5..f201ad3458777b22cb261a7bdcaa2e64180a9c4d 100644 (file)
--- a/board/altera/arria5-socdk/qts/iocsr_config.h
+++ b/board/altera/arria5-socdk/qts/iocsr_config.h
@@ -6,10 +6,10 @@
 #ifndef __SOCFPGA_IOCSR_CONFIG_H__
 #define __SOCFPGA_IOCSR_CONFIG_H__
 
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH     1337
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH     1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH     1528
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH     16766
+#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH        1337
+#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH        1719
+#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH        1528
+#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH        16766
 
 const unsigned long iocsr_scan_chain0_table[] = {
        0x00000000,

diff --git a/board/altera/arria5-socdk/qts/pll_config.h b/board/altera/arria5-socdk/qts/pll_config.h
index 6c83254344406d87f61e75fc771770aab5283b16..7fe290b28d96e00a8e1807bd45677c62f5079360 100644 (file)
--- a/board/altera/arria5-socdk/qts/pll_config.h
+++ b/board/altera/arria5-socdk/qts/pll_config.h
@@ -6,79 +6,79 @@
 #ifndef __SOCFPGA_PLL_CONFIG_H__
 #define __SOCFPGA_PLL_CONFIG_H__
 
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define CFG_HPS_DBCTRL_STAYOSC1 1
 
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 41
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 2
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 8
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CFG_HPS_MAINPLLGRP_VCO_NUMER 41
+#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 2
+#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 8
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
 
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 1
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 1
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 9
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define CFG_HPS_PERPLLGRP_VCO_DENOM 1
+#define CFG_HPS_PERPLLGRP_VCO_NUMER 79
+#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 1
+#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 9
+#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 4
+#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 1
+#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 1
+#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CFG_HPS_PERPLLGRP_SRC_NAND 2
+#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
 
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 127
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_VCO_DENOM 2
+#define CFG_HPS_SDRPLLGRP_VCO_NUMER 127
+#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
 
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1050000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 1066000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 350000000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 100000000
-#define CONFIG_HPS_CLK_CAN1_HZ 100000000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define CFG_HPS_CLK_OSC1_HZ 25000000
+#define CFG_HPS_CLK_OSC2_HZ 25000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1050000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_SDRVCO_HZ 1066000000
+#define CFG_HPS_CLK_EMAC0_HZ 250000000
+#define CFG_HPS_CLK_EMAC1_HZ 250000000
+#define CFG_HPS_CLK_USBCLK_HZ 200000000
+#define CFG_HPS_CLK_NAND_HZ 50000000
+#define CFG_HPS_CLK_SDMMC_HZ 200000000
+#define CFG_HPS_CLK_QSPI_HZ 350000000
+#define CFG_HPS_CLK_SPIM_HZ 200000000
+#define CFG_HPS_CLK_CAN0_HZ 100000000
+#define CFG_HPS_CLK_CAN1_HZ 100000000
+#define CFG_HPS_CLK_GPIODB_HZ 32000
+#define CFG_HPS_CLK_L4_MP_HZ 100000000
+#define CFG_HPS_CLK_L4_SP_HZ 100000000
 
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 0
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 2
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define CFG_HPS_ALTERAGRP_MPUCLK 0
+#define CFG_HPS_ALTERAGRP_MAINCLK 2
+#define CFG_HPS_ALTERAGRP_DBGATCLK 3
 
 
 #endif /* __SOCFPGA_PLL_CONFIG_H__ */

diff --git a/board/altera/arria5-socdk/qts/sdram_config.h b/board/altera/arria5-socdk/qts/sdram_config.h
index 927a7a4f8e042286352216c52b64239376755276..1d032e1af4bdb668dae5ac7c281e9fc6be9310e6 100644 (file)
--- a/board/altera/arria5-socdk/qts/sdram_config.h
+++ b/board/altera/arria5-socdk/qts/sdram_config.h
@@ -7,76 +7,76 @@
 #define __SOCFPGA_SDRAM_CONFIG_H__
 
 /* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR             0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP             0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH           0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP             0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER               0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN               1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                   1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                   8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN               1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT             10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH             2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS              3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS               10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                        1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS               15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH           8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH             40
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ                    0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                   1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                  0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                        6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                        19
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                        139
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD             8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI            4160
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP              8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR              8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR             4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                        19
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                 26
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT         3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT                512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                        0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST                     0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK           3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES       0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES   8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0      0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32     0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0       0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4      0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36     0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY         0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0        0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32       0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64       0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0   0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32  0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0    0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14   0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46   0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0               0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN               0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP             0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA          0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP             0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR                0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP                0xB00088
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH              0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP                0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER          0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                   0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN          1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                      1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                      8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                    2
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                   0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN          1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT                10
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH                2
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS         3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS          10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                   1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS          15
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH              8
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH                40
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                    0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ                       0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                      1
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                     0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                    7
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                   6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                   19
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                   139
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD                8
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI               4160
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP         8
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR         8
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR                4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                   19
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                    26
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT            3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT           512
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                    0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                   0
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST                        0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK              3
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES  0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES      8
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32        0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0  0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36        0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY            0x3FFD1088
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0   0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32  0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64  0x0101
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0      0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32     0x1EF84
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0       0x2020
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14      0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46      0xF800
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0          0x200
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN          0
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP                0x760210
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                    2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA             0
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP                0x980543
 
 /* Sequencer auto configuration */
 #define RW_MGR_ACTIVATE_0_AND_1        0x0D

diff --git a/board/altera/cyclone5-socdk/qts/iocsr_config.h b/board/altera/cyclone5-socdk/qts/iocsr_config.h
index 81c507b842bcbe01899d691e22ec609505c4f44d..a571fb3e509b360e2b8965ee41457bfcd1a28d35 100644 (file)
--- a/board/altera/cyclone5-socdk/qts/iocsr_config.h
+++ b/board/altera/cyclone5-socdk/qts/iocsr_config.h
@@ -6,10 +6,10 @@
 #ifndef __SOCFPGA_IOCSR_CONFIG_H__
 #define __SOCFPGA_IOCSR_CONFIG_H__
 
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH     764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH     1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH     955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH     16766
+#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH        764
+#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH        1719
+#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH        955
+#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH        16766
 
 const unsigned long iocsr_scan_chain0_table[] = {
        0x00000000,

diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h
index ae5cfab0cf706f8b40c9422dedb6cdbc5e704ec4..a46d124e9e99889f1a04a32b5a3b5d28e90a797c 100644 (file)
--- a/board/altera/cyclone5-socdk/qts/pll_config.h
+++ b/board/altera/cyclone5-socdk/qts/pll_config.h
@@ -6,79 +6,79 @@
 #ifndef __SOCFPGA_PLL_CONFIG_H__
 #define __SOCFPGA_PLL_CONFIG_H__
 
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define CFG_HPS_DBCTRL_STAYOSC1 1
 
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CFG_HPS_MAINPLLGRP_VCO_NUMER 73
+#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
+#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
 
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CFG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 1
+#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CFG_HPS_PERPLLGRP_SRC_NAND 2
+#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
 
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
 
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 370000000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 100000000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define CFG_HPS_CLK_OSC1_HZ 25000000
+#define CFG_HPS_CLK_OSC2_HZ 25000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1850000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_SDRVCO_HZ 800000000
+#define CFG_HPS_CLK_EMAC0_HZ 1953125
+#define CFG_HPS_CLK_EMAC1_HZ 250000000
+#define CFG_HPS_CLK_USBCLK_HZ 200000000
+#define CFG_HPS_CLK_NAND_HZ 50000000
+#define CFG_HPS_CLK_SDMMC_HZ 200000000
+#define CFG_HPS_CLK_QSPI_HZ 370000000
+#define CFG_HPS_CLK_SPIM_HZ 200000000
+#define CFG_HPS_CLK_CAN0_HZ 100000000
+#define CFG_HPS_CLK_CAN1_HZ 12500000
+#define CFG_HPS_CLK_GPIODB_HZ 32000
+#define CFG_HPS_CLK_L4_MP_HZ 100000000
+#define CFG_HPS_CLK_L4_SP_HZ 100000000
 
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 4
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
+#define CFG_HPS_ALTERAGRP_MPUCLK 1
+#define CFG_HPS_ALTERAGRP_MAINCLK 4
+#define CFG_HPS_ALTERAGRP_DBGATCLK 4
 
 
 #endif /* __SOCFPGA_PLL_CONFIG_H__ */

diff --git a/board/altera/cyclone5-socdk/qts/sdram_config.h b/board/altera/cyclone5-socdk/qts/sdram_config.h
index 8adbfec11f95d307170d89149a60ec0e6ae9d83a..e3a8cfbfb38cf79841fab5b75ca5775f625c0f68 100644 (file)
--- a/board/altera/cyclone5-socdk/qts/sdram_config.h
+++ b/board/altera/cyclone5-socdk/qts/sdram_config.h
@@ -7,76 +7,76 @@
 #define __SOCFPGA_SDRAM_CONFIG_H__
 
 /* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR             0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP             0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH           0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP             0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER               0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN               1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                   1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                   8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN               1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT             10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH             2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS              3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS               10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                        1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS               15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH           8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH             40
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ                    0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                   1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                  0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                        6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                        14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                        104
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                        3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD             6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI            3120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP              6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR              6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR             4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                        14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                        3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT         3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT                512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                        0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST                     0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK           3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES       0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES   8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0      0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32     0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0       0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4      0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36     0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY         0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0        0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32       0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64       0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0   0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32  0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0    0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14   0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46   0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0               0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN               0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP             0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA          0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP             0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR                0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP                0xB00088
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH              0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP                0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER          0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                   0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN          1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                      1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                      8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                    2
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                   0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN          1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT                10
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH                2
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS         3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS          10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                   1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS          15
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH              8
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH                40
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                    0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ                       0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                      1
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                     0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                    7
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                   6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                   14
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                   104
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                   3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD                6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI               3120
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP         6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR         6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR                4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                   14
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                    20
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                   3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT            3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT           512
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                    0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                   0
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST                        0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK              3
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES  0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES      8
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32        0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0  0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36        0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY            0x3FFD1088
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0   0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32  0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64  0x0101
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0      0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32     0x1EF84
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0       0x2020
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14      0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46      0xF800
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0          0x200
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN          0
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP                0x760210
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                    2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA             0
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP                0x980543
 
 /* Sequencer auto configuration */
 #define RW_MGR_ACTIVATE_0_AND_1        0x0D

diff --git a/board/aries/mcvevk/qts/iocsr_config.h b/board/aries/mcvevk/qts/iocsr_config.h
index e233d02b97db45f703a2cb05fa910665e8f7cc21..dbcc1d719d411f2ab742dde5308b4afc4769143f 100644 (file)
--- a/board/aries/mcvevk/qts/iocsr_config.h
+++ b/board/aries/mcvevk/qts/iocsr_config.h
@@ -6,10 +6,10 @@
 #ifndef __SOCFPGA_IOCSR_CONFIG_H__
 #define __SOCFPGA_IOCSR_CONFIG_H__
 
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH     764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH     1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH     955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH     16766
+#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH        764
+#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH        1719
+#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH        955
+#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH        16766
 
 const unsigned long iocsr_scan_chain0_table[] = {
        0x00000000,

diff --git a/board/aries/mcvevk/qts/pll_config.h b/board/aries/mcvevk/qts/pll_config.h
index 4fa868e458f0bdb601f2ef3f59c96ddb434fc10e..62cf6796afc96ab1f7735dacce9519d56dad4ff6 100644 (file)
--- a/board/aries/mcvevk/qts/pll_config.h
+++ b/board/aries/mcvevk/qts/pll_config.h
@@ -6,79 +6,79 @@
 #ifndef __SOCFPGA_PLL_CONFIG_H__
 #define __SOCFPGA_PLL_CONFIG_H__
 
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define CFG_HPS_DBCTRL_STAYOSC1 1
 
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
 
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CFG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 1
+#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 1
+#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CFG_HPS_PERPLLGRP_SRC_NAND 2
+#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
 
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
 
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
-#define CONFIG_HPS_CLK_EMAC1_HZ 1953125
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 3125000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 100000000
-#define CONFIG_HPS_CLK_CAN1_HZ 100000000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define CFG_HPS_CLK_OSC1_HZ 25000000
+#define CFG_HPS_CLK_OSC2_HZ 25000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_SDRVCO_HZ 800000000
+#define CFG_HPS_CLK_EMAC0_HZ 250000000
+#define CFG_HPS_CLK_EMAC1_HZ 1953125
+#define CFG_HPS_CLK_USBCLK_HZ 200000000
+#define CFG_HPS_CLK_NAND_HZ 50000000
+#define CFG_HPS_CLK_SDMMC_HZ 200000000
+#define CFG_HPS_CLK_QSPI_HZ 3125000
+#define CFG_HPS_CLK_SPIM_HZ 200000000
+#define CFG_HPS_CLK_CAN0_HZ 100000000
+#define CFG_HPS_CLK_CAN1_HZ 100000000
+#define CFG_HPS_CLK_GPIODB_HZ 32000
+#define CFG_HPS_CLK_L4_MP_HZ 100000000
+#define CFG_HPS_CLK_L4_SP_HZ 100000000
 
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define CFG_HPS_ALTERAGRP_MPUCLK 1
+#define CFG_HPS_ALTERAGRP_MAINCLK 3
+#define CFG_HPS_ALTERAGRP_DBGATCLK 3
 
 
 #endif /* __SOCFPGA_PLL_CONFIG_H__ */

diff --git a/board/aries/mcvevk/qts/sdram_config.h b/board/aries/mcvevk/qts/sdram_config.h
index fd72926a89e3900841f1f3d78f2c624c3ddd4a22..c6a24f5632a6bdacee99e395f79e166790ce7099 100644 (file)
--- a/board/aries/mcvevk/qts/sdram_config.h
+++ b/board/aries/mcvevk/qts/sdram_config.h
@@ -7,76 +7,76 @@
 #define __SOCFPGA_SDRAM_CONFIG_H__
 
 /* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR             0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP             0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH           0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP             0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER               0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN               0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                   0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                   8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN               1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT             10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH             2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS              3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS               10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                        1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS               15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH           8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH             32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ                    0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                   1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                  0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                        6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                        16
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                        140
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                        5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD             6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI            1560
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP              6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR              6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR             4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                        14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                        5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT         3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT                512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                        0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST                     0x0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK           3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES       0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES   8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0      0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32     0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0       0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4      0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36     0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY         0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0        0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32       0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64       0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0   0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32  0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0    0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14   0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46   0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0               0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN               0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP             0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA          0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP             0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR                0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP                0xB00088
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH              0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP                0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER          0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                   0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN          0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                      0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                      8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                    2
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                   0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN          1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT                10
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH                2
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS         3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS          10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                   1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS          15
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH              8
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH                32
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                    0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ                       0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                      1
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                     0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                    6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                   6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                   16
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                   140
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                   5
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD                6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI               1560
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP         6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR         6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR                4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                   14
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                    20
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                   5
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT            3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT           512
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                    0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                   0
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST                        0x0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK              3
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES  0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES      8
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32        0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0  0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36        0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY            0x3FFD1088
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0   0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32  0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64  0x0101
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0      0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32     0x1EF84
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0       0x2020
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14      0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46      0xF800
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0          0x200
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN          0
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP                0x760210
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                    2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA             0
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP                0x980543
 
 /* Sequencer auto configuration */
 #define RW_MGR_ACTIVATE_0_AND_1        0x0D

diff --git a/board/devboards/dbm-soc1/qts/iocsr_config.h b/board/devboards/dbm-soc1/qts/iocsr_config.h
index 99ed62bb503eb52188c9ce40f713a877a60e8e0b..56b2130671a36fc5dc2758590668c0c593ba25b5 100644 (file)
--- a/board/devboards/dbm-soc1/qts/iocsr_config.h
+++ b/board/devboards/dbm-soc1/qts/iocsr_config.h
@@ -6,10 +6,10 @@
 #ifndef __SOCFPGA_IOCSR_CONFIG_H__
 #define __SOCFPGA_IOCSR_CONFIG_H__
 
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH     764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH     1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH     955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH     16766
+#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH        764
+#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH        1719
+#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH        955
+#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH        16766
 
 const unsigned long iocsr_scan_chain0_table[] = {
        0x00000000,

diff --git a/board/devboards/dbm-soc1/qts/pll_config.h b/board/devboards/dbm-soc1/qts/pll_config.h
index f6ffa08654adaec313bf2948980e95b382e38721..104e324d8a4fe23cdba9288f4b64ca34a1ebe5f8 100644 (file)
--- a/board/devboards/dbm-soc1/qts/pll_config.h
+++ b/board/devboards/dbm-soc1/qts/pll_config.h
@@ -6,79 +6,79 @@
 #ifndef __SOCFPGA_PLL_CONFIG_H__
 #define __SOCFPGA_PLL_CONFIG_H__
 
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define CFG_HPS_DBCTRL_STAYOSC1 1
 
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
 
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CFG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CFG_HPS_PERPLLGRP_SRC_NAND 2
+#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
 
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
 
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 400000000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define CFG_HPS_CLK_OSC1_HZ 25000000
+#define CFG_HPS_CLK_OSC2_HZ 25000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_SDRVCO_HZ 800000000
+#define CFG_HPS_CLK_EMAC0_HZ 1953125
+#define CFG_HPS_CLK_EMAC1_HZ 250000000
+#define CFG_HPS_CLK_USBCLK_HZ 200000000
+#define CFG_HPS_CLK_NAND_HZ 50000000
+#define CFG_HPS_CLK_SDMMC_HZ 200000000
+#define CFG_HPS_CLK_QSPI_HZ 400000000
+#define CFG_HPS_CLK_SPIM_HZ 200000000
+#define CFG_HPS_CLK_CAN0_HZ 12500000
+#define CFG_HPS_CLK_CAN1_HZ 12500000
+#define CFG_HPS_CLK_GPIODB_HZ 32000
+#define CFG_HPS_CLK_L4_MP_HZ 100000000
+#define CFG_HPS_CLK_L4_SP_HZ 100000000
 
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define CFG_HPS_ALTERAGRP_MPUCLK 1
+#define CFG_HPS_ALTERAGRP_MAINCLK 3
+#define CFG_HPS_ALTERAGRP_DBGATCLK 3
 
 
 #endif /* __SOCFPGA_PLL_CONFIG_H__ */

diff --git a/board/devboards/dbm-soc1/qts/sdram_config.h b/board/devboards/dbm-soc1/qts/sdram_config.h
index 2022969bed9b89ac6e3081992d193b164b46845f..2c4559b1aad8151a34fa44c787f858f0d7bcd3ca 100644 (file)
--- a/board/devboards/dbm-soc1/qts/sdram_config.h
+++ b/board/devboards/dbm-soc1/qts/sdram_config.h
@@ -7,76 +7,76 @@
 #define __SOCFPGA_SDRAM_CONFIG_H__
 
 /* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR             0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP             0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH           0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP             0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER               0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN               0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                   0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                   8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN               1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT             10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH             2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS              3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS               10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                        1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS               15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH           8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH             32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ                    0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                   1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                  0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                        6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                        16
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                        140
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                        5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD             6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI            1560
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP              6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR              6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR             4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                        14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                        5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT         3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT                512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                        0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST                     0x0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK           3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES       0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES   8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0      0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32     0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0       0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4      0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36     0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY         0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0   0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32  0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0    0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14   0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46   0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0               0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN               0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP             0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA          0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP             0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR                0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP                0xB00088
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH              0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP                0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER          0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                   0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN          0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                      0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                      8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                    2
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                   0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN          1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT                10
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH                2
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS         3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS          10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                   1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS          15
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH              8
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH                32
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                    0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ                       0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                      1
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                     0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                    6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                   6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                   16
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                   140
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                   5
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD                6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI               1560
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP         6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR         6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR                4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                   14
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                    20
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                   5
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT            3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT           512
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                    0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                   0
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST                        0x0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK              3
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES  0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES      8
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32        0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0  0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36        0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY            0x3FFD1088
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0      0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32     0x1EF84
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0       0x2020
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14      0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46      0xF800
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0          0x200
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN          0
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP                0x760210
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                    2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA             0
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP                0x980543
 
 /* Sequencer auto configuration */
 #define RW_MGR_ACTIVATE_0_AND_1        0x0D

diff --git a/board/ebv/socrates/qts/iocsr_config.h b/board/ebv/socrates/qts/iocsr_config.h
index 18b9c6ce4dfc003cd5e74f1b8ff91e3756a3684e..c24b5cb5f0b237714dc8ecf896cd67dfabd6ec8e 100644 (file)
--- a/board/ebv/socrates/qts/iocsr_config.h
+++ b/board/ebv/socrates/qts/iocsr_config.h
@@ -6,10 +6,10 @@
 #ifndef __SOCFPGA_IOCSR_CONFIG_H__
 #define __SOCFPGA_IOCSR_CONFIG_H__
 
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH     764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH     1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH     955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH     16766
+#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH        764
+#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH        1719
+#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH        955
+#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH        16766
 
 const unsigned long iocsr_scan_chain0_table[] = {
        0x00000000,

diff --git a/board/ebv/socrates/qts/pll_config.h b/board/ebv/socrates/qts/pll_config.h
index 71d3674758fc6693583544ed0f4e5e1fe64a9164..eaa18c1c802c784f39e343265889155c1497baef 100644 (file)
--- a/board/ebv/socrates/qts/pll_config.h
+++ b/board/ebv/socrates/qts/pll_config.h
@@ -6,79 +6,79 @@
 #ifndef __SOCFPGA_PLL_CONFIG_H__
 #define __SOCFPGA_PLL_CONFIG_H__
 
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define CFG_HPS_DBCTRL_STAYOSC1 1
 
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
 
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CFG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 1
+#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CFG_HPS_PERPLLGRP_SRC_NAND 2
+#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
 
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 79
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_VCO_DENOM 2
+#define CFG_HPS_SDRPLLGRP_VCO_NUMER 79
+#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
 
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 400000000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 100000000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define CFG_HPS_CLK_OSC1_HZ 25000000
+#define CFG_HPS_CLK_OSC2_HZ 25000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_SDRVCO_HZ 666666666
+#define CFG_HPS_CLK_EMAC0_HZ 1953125
+#define CFG_HPS_CLK_EMAC1_HZ 250000000
+#define CFG_HPS_CLK_USBCLK_HZ 200000000
+#define CFG_HPS_CLK_NAND_HZ 50000000
+#define CFG_HPS_CLK_SDMMC_HZ 200000000
+#define CFG_HPS_CLK_QSPI_HZ 400000000
+#define CFG_HPS_CLK_SPIM_HZ 200000000
+#define CFG_HPS_CLK_CAN0_HZ 100000000
+#define CFG_HPS_CLK_CAN1_HZ 12500000
+#define CFG_HPS_CLK_GPIODB_HZ 32000
+#define CFG_HPS_CLK_L4_MP_HZ 100000000
+#define CFG_HPS_CLK_L4_SP_HZ 100000000
 
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define CFG_HPS_ALTERAGRP_MPUCLK 1
+#define CFG_HPS_ALTERAGRP_MAINCLK 3
+#define CFG_HPS_ALTERAGRP_DBGATCLK 3
 
 
 #endif /* __SOCFPGA_PLL_CONFIG_H__ */

diff --git a/board/ebv/socrates/qts/sdram_config.h b/board/ebv/socrates/qts/sdram_config.h
index 2f8465bf77cade45055c3d7de7a920ee2fe5401b..318ef0cd1dd5561d4a7e1fd37ad31059228e3cfb 100644 (file)
--- a/board/ebv/socrates/qts/sdram_config.h
+++ b/board/ebv/socrates/qts/sdram_config.h
@@ -7,76 +7,76 @@
 #define __SOCFPGA_SDRAM_CONFIG_H__
 
 /* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR             0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP             0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH           0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP             0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER               0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN               0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                   0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                   8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN               1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT             10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH             2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS              3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS               10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                        1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS               15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH           8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH             32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ                    0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                   1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                  0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                        6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                        14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                        117
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD             5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI            1300
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP              5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR              5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR             4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                        12
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                 17
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT         3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT                512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                        0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST                     0x0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK           3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES       0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES   8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0      0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32     0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0       0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4      0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36     0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY         0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0        0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32       0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64       0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0   0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32  0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0    0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14   0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46   0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0               0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN               0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP             0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA          0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP             0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR                0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP                0xB00088
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH              0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP                0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER          0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                   0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN          0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                      0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                      8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                    2
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                   0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN          1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT                10
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH                2
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS         3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS          10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                   1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS          15
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH              8
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH                32
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                    0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ                       0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                      1
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                     0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                    6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                   6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                   14
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                   117
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD                5
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI               1300
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP         5
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR         5
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR                4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                   12
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                    17
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT            3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT           512
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                    0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                   0
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST                        0x0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK              3
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES  0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES      8
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32        0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0  0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36        0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY            0x3FFD1088
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0   0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32  0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64  0x0101
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0      0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32     0x1EF84
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0       0x2020
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14      0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46      0xF800
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0          0x200
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN          0
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP                0x760210
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                    2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA             0
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP                0x980543
 
 /* Sequencer auto configuration */
 #define RW_MGR_ACTIVATE_0_AND_1        0x0D

diff --git a/board/is1/qts/iocsr_config.h b/board/is1/qts/iocsr_config.h
index 1d2774aa41a746728e4a27260b97cf158093d85c..e54af2caed49b5c1d7253f6e00a1898f9afbeb97 100644 (file)
--- a/board/is1/qts/iocsr_config.h
+++ b/board/is1/qts/iocsr_config.h
@@ -6,10 +6,10 @@
 #ifndef __SOCFPGA_IOCSR_CONFIG_H__
 #define __SOCFPGA_IOCSR_CONFIG_H__
 
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH     764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH     1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH     955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH     16766
+#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH        764
+#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH        1719
+#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH        955
+#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH        16766
 
 const unsigned long iocsr_scan_chain0_table[] = {
        0x00000000,

diff --git a/board/is1/qts/pll_config.h b/board/is1/qts/pll_config.h
index 218ab35c0424bd96b6d2cbd3f20a4d187cdde089..0a5f5dd196fb748744a44ef8a4b05e9ad0c6016b 100644 (file)
--- a/board/is1/qts/pll_config.h
+++ b/board/is1/qts/pll_config.h
@@ -6,79 +6,79 @@
 #ifndef __SOCFPGA_PLL_CONFIG_H__
 #define __SOCFPGA_PLL_CONFIG_H__
 
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define CFG_HPS_DBCTRL_STAYOSC1 1
 
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 59
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CFG_HPS_MAINPLLGRP_VCO_NUMER 59
+#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
+#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
 
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 39
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CFG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 39
+#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 4
+#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CFG_HPS_PERPLLGRP_SRC_NAND 2
+#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
 
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
 
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1500000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 488281
-#define CONFIG_HPS_CLK_SDMMC_HZ 1953125
-#define CONFIG_HPS_CLK_QSPI_HZ 375000000
-#define CONFIG_HPS_CLK_SPIM_HZ 12500000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define CFG_HPS_CLK_OSC1_HZ 25000000
+#define CFG_HPS_CLK_OSC2_HZ 25000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1500000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_SDRVCO_HZ 800000000
+#define CFG_HPS_CLK_EMAC0_HZ 250000000
+#define CFG_HPS_CLK_EMAC1_HZ 250000000
+#define CFG_HPS_CLK_USBCLK_HZ 200000000
+#define CFG_HPS_CLK_NAND_HZ 488281
+#define CFG_HPS_CLK_SDMMC_HZ 1953125
+#define CFG_HPS_CLK_QSPI_HZ 375000000
+#define CFG_HPS_CLK_SPIM_HZ 12500000
+#define CFG_HPS_CLK_CAN0_HZ 12500000
+#define CFG_HPS_CLK_CAN1_HZ 12500000
+#define CFG_HPS_CLK_GPIODB_HZ 32000
+#define CFG_HPS_CLK_L4_MP_HZ 100000000
+#define CFG_HPS_CLK_L4_SP_HZ 100000000
 
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 4
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
+#define CFG_HPS_ALTERAGRP_MPUCLK 1
+#define CFG_HPS_ALTERAGRP_MAINCLK 4
+#define CFG_HPS_ALTERAGRP_DBGATCLK 4
 
 
 #endif /* __SOCFPGA_PLL_CONFIG_H__ */

diff --git a/board/is1/qts/sdram_config.h b/board/is1/qts/sdram_config.h
index 2573171abeb161250eaf138e9d2fb6c0e3101f21..d8521a7e024827e2d607e6dffecb4f7cdfecd6b4 100644 (file)
--- a/board/is1/qts/sdram_config.h
+++ b/board/is1/qts/sdram_config.h
@@ -7,76 +7,76 @@
 #define __SOCFPGA_SDRAM_CONFIG_H__
 
 /* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR             0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP             0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH           0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP             0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER               0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN               0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                   0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                   8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN               1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT             10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH             1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS              3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS               10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                        1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS               14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH           8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH             16
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ                    0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                   1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                  0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                        6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                        16
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                        64
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                        3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD             6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI            3120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP              6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR              6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR             4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                        14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                        3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT         3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT                512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                        0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST                     0x777
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK           3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES       0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES   8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0      0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32     0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0       0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4      0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36     0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY         0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0   0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32  0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0    0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14   0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46   0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0               0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN               0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP             0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA          0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP             0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR                0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP                0xB00088
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH              0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP                0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER          0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                   0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN          0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                      0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                      8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                    2
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                   0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN          1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT                10
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH                1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS         3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS          10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                   1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS          14
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH              8
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH                16
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                    0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ                       0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                      1
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                     0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                    7
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                   6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                   16
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                   64
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                   3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD                6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI               3120
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP         6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR         6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR                4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                   14
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                    20
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                   3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT            3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT           512
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                    0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                   0
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST                        0x777
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK              3
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES  0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES      8
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32        0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0  0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36        0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY            0x3FFD1088
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0      0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32     0x1EF84
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0       0x2020
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14      0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46      0xF800
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0          0x200
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN          0
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP                0x760210
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                    2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA             0
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP                0x980543
 
 /* Sequencer auto configuration */
 #define RW_MGR_ACTIVATE_0_AND_1        0x0D

diff --git a/board/keymile/secu1/qts/iocsr_config.h b/board/keymile/secu1/qts/iocsr_config.h
index 7640c56db16665f488f0d7af4b06653029377e38..9f05fce8b30b473f55ed2e73421b0d8ed2d7f185 100644 (file)
--- a/board/keymile/secu1/qts/iocsr_config.h
+++ b/board/keymile/secu1/qts/iocsr_config.h
@@ -6,10 +6,10 @@
 #ifndef __SOCFPGA_IOCSR_CONFIG_H__
 #define __SOCFPGA_IOCSR_CONFIG_H__
 
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH     1337
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH     1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH     1528
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH     16766
+#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH        1337
+#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH        1719
+#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH        1528
+#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH        16766
 
 const unsigned long iocsr_scan_chain0_table[] = {
        0x00100000,

diff --git a/board/keymile/secu1/qts/pll_config.h b/board/keymile/secu1/qts/pll_config.h
index f0c31860ca4b42680f4348bf70620cf6a40219b3..7bc704a1820d3937c4d09454c05d7338c8e71b39 100644 (file)
--- a/board/keymile/secu1/qts/pll_config.h
+++ b/board/keymile/secu1/qts/pll_config.h
@@ -6,78 +6,78 @@
 #ifndef __SOCFPGA_PLL_CONFIG_H__
 #define __SOCFPGA_PLL_CONFIG_H__
 
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define CFG_HPS_DBCTRL_STAYOSC1 1
 
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CFG_HPS_MAINPLLGRP_VCO_NUMER 39
+#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
 
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 24
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 7
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 1
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CFG_HPS_PERPLLGRP_VCO_NUMER 24
+#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 7
+#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_DIV_USBCLK 4
+#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CFG_HPS_PERPLLGRP_SRC_SDMMC 1
+#define CFG_HPS_PERPLLGRP_SRC_NAND 2
+#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
 
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 14
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CFG_HPS_SDRPLLGRP_VCO_NUMER 14
+#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
 
-#define CONFIG_HPS_CLK_OSC1_HZ 40000000
-#define CONFIG_HPS_CLK_OSC2_HZ 40000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 600000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
-#define CONFIG_HPS_CLK_EMAC1_HZ 1953125
-#define CONFIG_HPS_CLK_USBCLK_HZ 12500000
-#define CONFIG_HPS_CLK_NAND_HZ 31250000
-#define CONFIG_HPS_CLK_SDMMC_HZ 3125000
-#define CONFIG_HPS_CLK_QSPI_HZ 3125000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define CFG_HPS_CLK_OSC1_HZ 40000000
+#define CFG_HPS_CLK_OSC2_HZ 40000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_SDRVCO_HZ 600000000
+#define CFG_HPS_CLK_EMAC0_HZ 250000000
+#define CFG_HPS_CLK_EMAC1_HZ 1953125
+#define CFG_HPS_CLK_USBCLK_HZ 12500000
+#define CFG_HPS_CLK_NAND_HZ 31250000
+#define CFG_HPS_CLK_SDMMC_HZ 3125000
+#define CFG_HPS_CLK_QSPI_HZ 3125000
+#define CFG_HPS_CLK_SPIM_HZ 200000000
+#define CFG_HPS_CLK_CAN0_HZ 12500000
+#define CFG_HPS_CLK_CAN1_HZ 12500000
+#define CFG_HPS_CLK_GPIODB_HZ 32000
+#define CFG_HPS_CLK_L4_MP_HZ 100000000
+#define CFG_HPS_CLK_L4_SP_HZ 100000000
 
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define CFG_HPS_ALTERAGRP_MPUCLK 1
+#define CFG_HPS_ALTERAGRP_MAINCLK 3
+#define CFG_HPS_ALTERAGRP_DBGATCLK 3
 
 #endif /* __SOCFPGA_PLL_CONFIG_H__ */

diff --git a/board/keymile/secu1/qts/sdram_config.h b/board/keymile/secu1/qts/sdram_config.h
index b0ff86ef3814851fc481a8d4799ed5c1a4aa0be3..a0ce0b26ca912248facf832dbbb7d4e08085f2b0 100644 (file)
--- a/board/keymile/secu1/qts/sdram_config.h
+++ b/board/keymile/secu1/qts/sdram_config.h
@@ -8,76 +8,76 @@
 #define __SOCFPGA_SDRAM_CONFIG_H__
 
 /* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR             0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP             0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH           0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP             0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER               0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN               0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                   0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                   8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN               1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT             10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH             2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS              3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS               10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                        1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS               14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH           8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH             32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ                    0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                   1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                  0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                        16
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                        60
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD             5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI            2341
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP              5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR              5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR             2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                        2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                        13
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                 17
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                        3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT         3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT                200
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 3
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 3
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 3
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                        0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST                     0x0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK           3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES       0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES   8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0      0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32     0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0       0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4      0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36     0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY         0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0   0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32  0x10441
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0    0x78
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14   0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46   0x0
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0               0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN               0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP             0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA          0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP             0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR                0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP                0xB00088
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH              0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP                0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER          0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                   0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN          0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                      0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                      8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                    1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                   0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN          1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT                10
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH                2
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS         3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS          10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                   1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS          14
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH              8
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH                32
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                    0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ                       0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                      1
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                     0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                    5
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                   16
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                   60
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD                5
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI               2341
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP         5
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR         5
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR                2
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                   2
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                   13
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                    17
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                   3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT            3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT           200
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 3
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 3
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 3
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                    0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                   0
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST                        0x0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK              3
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES  0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES      8
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32        0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0  0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36        0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY            0x0
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0      0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32     0x10441
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0       0x78
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14      0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46      0x0
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0          0x200
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN          0
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP                0x760210
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                    2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA             0
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP                0x980543
 
 /* Sequencer auto configuration */
 #define RW_MGR_ACTIVATE_0_AND_1        0x11

diff --git a/board/softing/vining_fpga/qts/iocsr_config.h b/board/softing/vining_fpga/qts/iocsr_config.h
index 8c78aecdd3de573179a75f46fc4a3f653cb06b15..4059ed5ad12a1071f0e014bf4e6eebc4874cef43 100644 (file)
--- a/board/softing/vining_fpga/qts/iocsr_config.h
+++ b/board/softing/vining_fpga/qts/iocsr_config.h
@@ -6,10 +6,10 @@
 #ifndef __SOCFPGA_IOCSR_CONFIG_H__
 #define __SOCFPGA_IOCSR_CONFIG_H__
 
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH     764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH     1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH     955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH     16766
+#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH        764
+#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH        1719
+#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH        955
+#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH        16766
 
 const unsigned long iocsr_scan_chain0_table[] = {
        0x00000000,

diff --git a/board/softing/vining_fpga/qts/pll_config.h b/board/softing/vining_fpga/qts/pll_config.h
index fa0461833694b97c16a8187eded81a5d2fcb2871..40bc8f7f7c12d3d266cb683c9682921707ec4ac3 100644 (file)
--- a/board/softing/vining_fpga/qts/pll_config.h
+++ b/board/softing/vining_fpga/qts/pll_config.h
@@ -6,79 +6,79 @@
 #ifndef __SOCFPGA_PLL_CONFIG_H__
 #define __SOCFPGA_PLL_CONFIG_H__
 
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define CFG_HPS_DBCTRL_STAYOSC1 1
 
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
+#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
 
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CFG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CFG_HPS_PERPLLGRP_SRC_NAND 2
+#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
 
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
 
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 488281
-#define CONFIG_HPS_CLK_SDMMC_HZ 1953125
-#define CONFIG_HPS_CLK_QSPI_HZ 320000000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define CFG_HPS_CLK_OSC1_HZ 25000000
+#define CFG_HPS_CLK_OSC2_HZ 25000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_SDRVCO_HZ 800000000
+#define CFG_HPS_CLK_EMAC0_HZ 250000000
+#define CFG_HPS_CLK_EMAC1_HZ 250000000
+#define CFG_HPS_CLK_USBCLK_HZ 200000000
+#define CFG_HPS_CLK_NAND_HZ 488281
+#define CFG_HPS_CLK_SDMMC_HZ 1953125
+#define CFG_HPS_CLK_QSPI_HZ 320000000
+#define CFG_HPS_CLK_SPIM_HZ 200000000
+#define CFG_HPS_CLK_CAN0_HZ 12500000
+#define CFG_HPS_CLK_CAN1_HZ 12500000
+#define CFG_HPS_CLK_GPIODB_HZ 32000
+#define CFG_HPS_CLK_L4_MP_HZ 100000000
+#define CFG_HPS_CLK_L4_SP_HZ 100000000
 
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define CFG_HPS_ALTERAGRP_MPUCLK 1
+#define CFG_HPS_ALTERAGRP_MAINCLK 3
+#define CFG_HPS_ALTERAGRP_DBGATCLK 3
 
 
 #endif /* __SOCFPGA_PLL_CONFIG_H__ */

diff --git a/board/softing/vining_fpga/qts/sdram_config.h b/board/softing/vining_fpga/qts/sdram_config.h
index ec067eb473d1fcb1a11599d2e08fc3258a080f29..27e3f3b2a5700245ad0212510fc3436342e0ead8 100644 (file)
--- a/board/softing/vining_fpga/qts/sdram_config.h
+++ b/board/softing/vining_fpga/qts/sdram_config.h
@@ -7,76 +7,76 @@
 #define __SOCFPGA_SDRAM_CONFIG_H__
 
 /* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR             0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP             0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH           0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP             0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER               0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN               0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                   0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                   8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN               1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT             10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH             2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS              3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS               10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                        1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS               15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH           8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH             32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ                    0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                   1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                  0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                        6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                        16
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                        104
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                        6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD             6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI            1560
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP              6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR              6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR             4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                        14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                        6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT         3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT                512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                        0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST                     0x0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK           3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES       0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES   8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0      0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32     0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0       0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4      0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36     0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY         0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0                0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32       0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64       0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0   0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32  0x10441
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0    0x78
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14   0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46   0x0
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0               0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN               0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP             0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA          0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP             0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR                0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP                0xB00088
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH              0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP                0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER          0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                   0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN          0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                      0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                      8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                    2
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                   0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN          1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT                10
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH                2
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS         3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS          10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                   1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS          15
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH              8
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH                32
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                    0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ                       0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                      1
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                     0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                    6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                   6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                   16
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                   104
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                   6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD                6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI               1560
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP         6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR         6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR                4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                   14
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                    20
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                   6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT            3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT           512
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                    0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                   0
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST                        0x0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK              3
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES  0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES      8
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32        0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0  0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36        0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY            0x0
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0           0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32  0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64  0x0101
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0      0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32     0x10441
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0       0x78
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14      0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46      0x0
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0          0x200
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN          0
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP                0x760210
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                    2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA             0
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP                0x980543
 
 /* Sequencer auto configuration */
 #define RW_MGR_ACTIVATE_0_AND_1        0x0D

diff --git a/board/sr1500/qts/iocsr_config.h b/board/sr1500/qts/iocsr_config.h
index b3b167fa7fc06da8cc9039919d4846b616d2fd51..2622b960314deac89a97dd3e6c8b7242be1654ae 100644 (file)
--- a/board/sr1500/qts/iocsr_config.h
+++ b/board/sr1500/qts/iocsr_config.h
@@ -6,10 +6,10 @@
 #ifndef __SOCFPGA_IOCSR_CONFIG_H__
 #define __SOCFPGA_IOCSR_CONFIG_H__
 
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH     764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH     1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH     955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH     16766
+#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH        764
+#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH        1719
+#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH        955
+#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH        16766
 
 const unsigned long iocsr_scan_chain0_table[] = {
        0x00100000,

diff --git a/board/sr1500/qts/pll_config.h b/board/sr1500/qts/pll_config.h
index 02f068f7424409793d48a15a75f73c812dd464ff..885fe91eebab27e77b5314148105be7e9e1e92b4 100644 (file)
--- a/board/sr1500/qts/pll_config.h
+++ b/board/sr1500/qts/pll_config.h
@@ -6,79 +6,79 @@
 #ifndef __SOCFPGA_PLL_CONFIG_H__
 #define __SOCFPGA_PLL_CONFIG_H__
 
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define CFG_HPS_DBCTRL_STAYOSC1 1
 
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
 
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CFG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 4
+#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CFG_HPS_PERPLLGRP_SRC_NAND 2
+#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
 
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
 
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 400000000
-#define CONFIG_HPS_CLK_SPIM_HZ 12500000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define CFG_HPS_CLK_OSC1_HZ 25000000
+#define CFG_HPS_CLK_OSC2_HZ 25000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_SDRVCO_HZ 800000000
+#define CFG_HPS_CLK_EMAC0_HZ 1953125
+#define CFG_HPS_CLK_EMAC1_HZ 250000000
+#define CFG_HPS_CLK_USBCLK_HZ 200000000
+#define CFG_HPS_CLK_NAND_HZ 50000000
+#define CFG_HPS_CLK_SDMMC_HZ 200000000
+#define CFG_HPS_CLK_QSPI_HZ 400000000
+#define CFG_HPS_CLK_SPIM_HZ 12500000
+#define CFG_HPS_CLK_CAN0_HZ 12500000
+#define CFG_HPS_CLK_CAN1_HZ 12500000
+#define CFG_HPS_CLK_GPIODB_HZ 32000
+#define CFG_HPS_CLK_L4_MP_HZ 100000000
+#define CFG_HPS_CLK_L4_SP_HZ 100000000
 
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define CFG_HPS_ALTERAGRP_MPUCLK 1
+#define CFG_HPS_ALTERAGRP_MAINCLK 3
+#define CFG_HPS_ALTERAGRP_DBGATCLK 3
 
 
 #endif /* __SOCFPGA_PLL_CONFIG_H__ */

diff --git a/board/sr1500/qts/sdram_config.h b/board/sr1500/qts/sdram_config.h
index d25354bb49cd0ec2d804871f46ca7d7d25ac3cb0..3438221d686382b19b27dd594beb69597db71123 100644 (file)
--- a/board/sr1500/qts/sdram_config.h
+++ b/board/sr1500/qts/sdram_config.h
@@ -7,76 +7,76 @@
 #define __SOCFPGA_SDRAM_CONFIG_H__
 
 /* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR             0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP             0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH           0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP             0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER               0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN               0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                   0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                   8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN               1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT             10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH             2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS              3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS               10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                        1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS               15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH           8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH             32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ                    0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                   1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                  0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                        6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                        16
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                        140
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                        5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD             6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI            1560
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP              6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR              6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR             4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                        14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                        5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT         3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT                512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                        0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST                     0x330
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK           3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES       0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES   8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0      0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32     0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0       0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4      0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36     0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY         0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0        0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32       0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64       0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0   0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32  0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0    0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14   0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46   0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0               0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN               0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP             0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA          0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP             0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR                0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP                0xB00088
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH              0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP                0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER          0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                   0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN          0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                      0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                      8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                    2
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                   0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN          1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT                10
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH                2
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS         3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS          10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                   1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS          15
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH              8
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH                32
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                    0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ                       0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                      1
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                     0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                    6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                   6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                   16
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                   140
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                   5
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD                6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI               1560
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP         6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR         6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR                4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                   14
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                    20
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                   5
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT            3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT           512
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                    0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                   0
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST                        0x330
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK              3
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES  0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES      8
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32        0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0  0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36        0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY            0x3FFD1088
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0   0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32  0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64  0x0101
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0      0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32     0x1EF84
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0       0x2020
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14      0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46      0xF800
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0          0x200
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN          0
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP                0x760210
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                    2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA             0
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP                0x980543
 
 /* Sequencer auto configuration */
 #define RW_MGR_ACTIVATE_0_AND_1        0x0D

diff --git a/board/terasic/de0-nano-soc/qts/iocsr_config.h b/board/terasic/de0-nano-soc/qts/iocsr_config.h
index 6ff5bd57112af267fa1f58613f14a25920f68f0d..b856474b7706c8ae85a84cdd4a06354920892387 100644 (file)
--- a/board/terasic/de0-nano-soc/qts/iocsr_config.h
+++ b/board/terasic/de0-nano-soc/qts/iocsr_config.h
@@ -6,10 +6,10 @@
 #ifndef __SOCFPGA_IOCSR_CONFIG_H__
 #define __SOCFPGA_IOCSR_CONFIG_H__
 
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH     764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH     1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH     955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH     16766
+#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH        764
+#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH        1719
+#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH        955
+#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH        16766
 
 const unsigned long iocsr_scan_chain0_table[] = {
        0x00000000,

diff --git a/board/terasic/de0-nano-soc/qts/pll_config.h b/board/terasic/de0-nano-soc/qts/pll_config.h
index e439336d45ab6f5fef73d0561dcb07a1f26af670..36d8fd1df2c15cdcdf0fa4618e0ab2f05a004655 100644 (file)
--- a/board/terasic/de0-nano-soc/qts/pll_config.h
+++ b/board/terasic/de0-nano-soc/qts/pll_config.h
@@ -6,78 +6,78 @@
 #ifndef _PRELOADER_PLL_CONFIG_H_
 #define _PRELOADER_PLL_CONFIG_H_
 
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define CFG_HPS_DBCTRL_STAYOSC1 1
 
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 18
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CFG_HPS_MAINPLLGRP_VCO_NUMER 73
+#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 18
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
 
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 19
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CFG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 19
+#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CFG_HPS_PERPLLGRP_SRC_NAND 2
+#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
 
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
 
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 3613281
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define CFG_HPS_CLK_OSC1_HZ 25000000
+#define CFG_HPS_CLK_OSC2_HZ 25000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1850000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_SDRVCO_HZ 800000000
+#define CFG_HPS_CLK_EMAC0_HZ 1953125
+#define CFG_HPS_CLK_EMAC1_HZ 250000000
+#define CFG_HPS_CLK_USBCLK_HZ 200000000
+#define CFG_HPS_CLK_NAND_HZ 50000000
+#define CFG_HPS_CLK_SDMMC_HZ 200000000
+#define CFG_HPS_CLK_QSPI_HZ 3613281
+#define CFG_HPS_CLK_SPIM_HZ 200000000
+#define CFG_HPS_CLK_CAN0_HZ 12500000
+#define CFG_HPS_CLK_CAN1_HZ 12500000
+#define CFG_HPS_CLK_GPIODB_HZ 32000
+#define CFG_HPS_CLK_L4_MP_HZ 100000000
+#define CFG_HPS_CLK_L4_SP_HZ 100000000
 
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 4
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
+#define CFG_HPS_ALTERAGRP_MPUCLK 1
+#define CFG_HPS_ALTERAGRP_MAINCLK 4
+#define CFG_HPS_ALTERAGRP_DBGATCLK 4
 
 #endif /* _PRELOADER_PLL_CONFIG_H_ */

diff --git a/board/terasic/de0-nano-soc/qts/sdram_config.h b/board/terasic/de0-nano-soc/qts/sdram_config.h
index 0504dd688f9b9d7422d16f764f06e4905eebfd5c..3fb2f2a58b4d3ed2cee9b0eeaea9d223be37aa3f 100644 (file)
--- a/board/terasic/de0-nano-soc/qts/sdram_config.h
+++ b/board/terasic/de0-nano-soc/qts/sdram_config.h
@@ -5,80 +5,80 @@
 #ifndef __SDRAM_CONFIG_H
 #define __SDRAM_CONFIG_H
 
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                   8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER               0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                   0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN               0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN               1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT             10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                        0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                        7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                  0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                        3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                        15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                        120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI            3120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD             6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP              6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR              6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR             4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                        3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                        14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT                512
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT         3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES       0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES   8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS               10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS               15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS              3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                        1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH             32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH           8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK           3
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA          0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH             2
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN               0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                        0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY         0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0   0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32  0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0    0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14   0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46   0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0               0x200
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                    2
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                      8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER          0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                      0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN          0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN          1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT                10
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                   0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                   0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                   7
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                     0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                    7
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                   3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                   15
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                   120
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI               3120
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD                6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP         6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR         6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR                4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                   3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                   14
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                    20
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT           512
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT            3
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES  0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES      8
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS          10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS          15
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS         3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                   1
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH                32
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH              8
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                    0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK              3
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                    2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA             0
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH                2
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN          0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                   0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                    0
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY            0x3FFD1088
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0      0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32     0x1EF84
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0       0x2020
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14      0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46      0xF800
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0          0x200
 
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH           0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP             0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP             0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP             0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP             0x980543
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR             0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0      0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32     0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0       0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4      0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36     0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0        0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ                    0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                   1
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED      0x1
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED     0x1
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED   0x3
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST                     0x311
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH              0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP                0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP                0xB00088
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP                0x760210
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP                0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR                0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32        0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0  0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36        0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0   0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ                       0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                      1
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED 0x1
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED        0x1
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED      0x3
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST                        0x311
 
 /* Sequencer auto configuration */
 #define RW_MGR_ACTIVATE_0_AND_1 0x0D

diff --git a/board/terasic/de1-soc/qts/iocsr_config.h b/board/terasic/de1-soc/qts/iocsr_config.h
index c65183ed8c086cbe36c52e95443bfdac20dd1bc3..359fd0e4173b2a8abe25b83928616e54ddb08abe 100644 (file)
--- a/board/terasic/de1-soc/qts/iocsr_config.h
+++ b/board/terasic/de1-soc/qts/iocsr_config.h
@@ -6,10 +6,10 @@
 #ifndef __SOCFPGA_IOCSR_CONFIG_H__
 #define __SOCFPGA_IOCSR_CONFIG_H__
 
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH     764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH     1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH     955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH     16766
+#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH        764
+#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH        1719
+#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH        955
+#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH        16766
 
 const unsigned long iocsr_scan_chain0_table[] = {
        0x00000000,

diff --git a/board/terasic/de1-soc/qts/pll_config.h b/board/terasic/de1-soc/qts/pll_config.h
index 4544f926935ae977b44d17daee2983e2e24ba663..2811e04c48076bbf619d513a2173cca1e5efac34 100644 (file)
--- a/board/terasic/de1-soc/qts/pll_config.h
+++ b/board/terasic/de1-soc/qts/pll_config.h
@@ -6,85 +6,85 @@
 #ifndef __SOCFPGA_PLL_CONFIG_H__
 #define __SOCFPGA_PLL_CONFIG_H__
 
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define CFG_HPS_DBCTRL_STAYOSC1 1
 
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
 
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CFG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CFG_HPS_PERPLLGRP_SRC_NAND 2
+#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
 
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
 
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 400000000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define CFG_HPS_CLK_OSC1_HZ 25000000
+#define CFG_HPS_CLK_OSC2_HZ 25000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_SDRVCO_HZ 800000000
+#define CFG_HPS_CLK_OSC1_HZ 25000000
+#define CFG_HPS_CLK_OSC2_HZ 25000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_EMAC0_HZ 1953125
+#define CFG_HPS_CLK_EMAC1_HZ 250000000
+#define CFG_HPS_CLK_USBCLK_HZ 200000000
+#define CFG_HPS_CLK_NAND_HZ 50000000
+#define CFG_HPS_CLK_SDMMC_HZ 200000000
+#define CFG_HPS_CLK_QSPI_HZ 400000000
+#define CFG_HPS_CLK_SPIM_HZ 200000000
+#define CFG_HPS_CLK_CAN0_HZ 12500000
+#define CFG_HPS_CLK_CAN1_HZ 12500000
+#define CFG_HPS_CLK_GPIODB_HZ 32000
+#define CFG_HPS_CLK_L4_MP_HZ 100000000
+#define CFG_HPS_CLK_L4_SP_HZ 100000000
 
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define CFG_HPS_ALTERAGRP_MPUCLK 1
+#define CFG_HPS_ALTERAGRP_MAINCLK 3
+#define CFG_HPS_ALTERAGRP_DBGATCLK 3
 
 
 #endif /* __SOCFPGA_PLL_CONFIG_H__ */

diff --git a/board/terasic/de1-soc/qts/sdram_config.h b/board/terasic/de1-soc/qts/sdram_config.h
index c60426f2ff669b6c09caa9d81e40ed339bbee085..7b0ff2ce01bc331bb42f174c149d187342eb90b9 100644 (file)
--- a/board/terasic/de1-soc/qts/sdram_config.h
+++ b/board/terasic/de1-soc/qts/sdram_config.h
@@ -7,76 +7,76 @@
 #define __SOCFPGA_SDRAM_CONFIG_H__
 
 /* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR             0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP             0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH           0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP             0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER               0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN               0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                   0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                   8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN               1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT             10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH             2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS              3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS               10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                        1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS               15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH           8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH             32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK           3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ                    0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                   1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                  0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                        7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                        18
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                        120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                        3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD             6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI            3120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP              6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR              6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR             4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                        15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                        3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT         3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT                200
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                        0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST                     0x0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES       0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES   8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0      0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32     0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0       0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4      0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36     0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY         0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0   0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32  0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0    0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14   0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46   0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0               0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN               0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP             0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA          0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP             0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR                0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP                0xB00088
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH              0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP                0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER          0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                   0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN          0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                      0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                      8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                    2
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                   0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN          1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT                10
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH                2
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS         3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS          10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                   1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS          15
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH              8
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH                32
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                    0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK              3
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ                       0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                      1
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                     0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                    7
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                   7
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                   18
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                   120
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                   3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD                6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI               3120
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP         6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR         6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR                4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                   15
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                    20
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                   3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT            3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT           200
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                    0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                   0
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST                        0x0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES  0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES      8
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32        0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0  0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36        0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY            0x3FFD1088
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0      0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32     0x1EF84
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0       0x2020
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14      0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46      0xF800
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0          0x200
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN          0
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP                0x760210
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                    2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA             0
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP                0x980543
 
 /* Sequencer auto configuration */
 #define RW_MGR_ACTIVATE_0_AND_1        0x0D

diff --git a/board/terasic/de10-nano/qts/iocsr_config.h b/board/terasic/de10-nano/qts/iocsr_config.h
index bc5b7a07c7d6f71b4291b35d2c0a055a4d4da7ad..a889d3da348517a1cf486e40174d221913f11b57 100644 (file)
--- a/board/terasic/de10-nano/qts/iocsr_config.h
+++ b/board/terasic/de10-nano/qts/iocsr_config.h
@@ -6,10 +6,10 @@
 #ifndef __SOCFPGA_IOCSR_CONFIG_H__
 #define __SOCFPGA_IOCSR_CONFIG_H__
 
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH     764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH     1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH     955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH     16766
+#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH        764
+#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH        1719
+#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH        955
+#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH        16766
 
 const unsigned long iocsr_scan_chain0_table[] = {
        0x00000000,

diff --git a/board/terasic/de10-nano/qts/pll_config.h b/board/terasic/de10-nano/qts/pll_config.h
index 854936b2a33acc55a339690180c61c3eb42a2226..192ffb4e27b22c537827cee73bf1462be238a71d 100644 (file)
--- a/board/terasic/de10-nano/qts/pll_config.h
+++ b/board/terasic/de10-nano/qts/pll_config.h
@@ -6,79 +6,79 @@
 #ifndef __SOCFPGA_PLL_CONFIG_H__
 #define __SOCFPGA_PLL_CONFIG_H__
 
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define CFG_HPS_DBCTRL_STAYOSC1 1
 
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
 
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 19
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CFG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 19
+#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CFG_HPS_PERPLLGRP_SRC_NAND 2
+#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
 
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
 
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 3125000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define CFG_HPS_CLK_OSC1_HZ 25000000
+#define CFG_HPS_CLK_OSC2_HZ 25000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_SDRVCO_HZ 800000000
+#define CFG_HPS_CLK_EMAC0_HZ 1953125
+#define CFG_HPS_CLK_EMAC1_HZ 250000000
+#define CFG_HPS_CLK_USBCLK_HZ 200000000
+#define CFG_HPS_CLK_NAND_HZ 50000000
+#define CFG_HPS_CLK_SDMMC_HZ 200000000
+#define CFG_HPS_CLK_QSPI_HZ 3125000
+#define CFG_HPS_CLK_SPIM_HZ 200000000
+#define CFG_HPS_CLK_CAN0_HZ 12500000
+#define CFG_HPS_CLK_CAN1_HZ 12500000
+#define CFG_HPS_CLK_GPIODB_HZ 32000
+#define CFG_HPS_CLK_L4_MP_HZ 100000000
+#define CFG_HPS_CLK_L4_SP_HZ 100000000
 
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define CFG_HPS_ALTERAGRP_MPUCLK 1
+#define CFG_HPS_ALTERAGRP_MAINCLK 3
+#define CFG_HPS_ALTERAGRP_DBGATCLK 3
 
 
 #endif /* __SOCFPGA_PLL_CONFIG_H__ */

diff --git a/board/terasic/de10-nano/qts/sdram_config.h b/board/terasic/de10-nano/qts/sdram_config.h
index 26910ef348b79bd5340ac189785e8d58b3b81870..abf29f25c1a4659e43d6b5eeb1e1bc709199f8b3 100644 (file)
--- a/board/terasic/de10-nano/qts/sdram_config.h
+++ b/board/terasic/de10-nano/qts/sdram_config.h
@@ -7,76 +7,76 @@
 #define __SOCFPGA_SDRAM_CONFIG_H__
 
 /* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR             0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP             0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH           0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP             0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER               0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN               0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                   0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                   8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN               1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT             10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH             2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS              3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS               10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                        1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS               15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH           8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH             32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ                    0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                   1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                  0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                        7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                        15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                        120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                        3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD             6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI            3120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP              6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR              6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR             4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                        14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                        3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT         3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT                512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                        0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST                     0x1FF
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK           3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES       0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES   8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0      0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32     0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0       0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4      0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36     0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY         0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0   0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32  0x10441
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0    0x78
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14   0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46   0x0
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0               0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN               0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP             0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA          0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP             0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR                0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP                0xB00088
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH              0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP                0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER          0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                   0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN          0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                      0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                      8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                    2
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                   0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN          1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT                10
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH                2
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS         3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS          10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                   1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS          15
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH              8
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH                32
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                    0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ                       0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                      1
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                     0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                    7
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                   7
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                   15
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                   120
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                   3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD                6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI               3120
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP         6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR         6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR                4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                   14
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                    20
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                   3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT            3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT           512
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                    0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                   0
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST                        0x1FF
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK              3
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES  0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES      8
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32        0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0  0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36        0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY            0x0
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0      0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32     0x10441
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0       0x78
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14      0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46      0x0
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0          0x200
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN          0
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP                0x760210
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                    2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA             0
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP                0x980543
 
 /* Sequencer auto configuration */
 #define RW_MGR_ACTIVATE_0_AND_1        0x0D

diff --git a/board/terasic/de10-standard/qts/iocsr_config.h b/board/terasic/de10-standard/qts/iocsr_config.h
index c062b5521fd13aa97c0ea0e1bfbf3efe7b22528b..4aed74e8b2986e1eeb2ff7b203b9e1d62da9ccad 100644 (file)
--- a/board/terasic/de10-standard/qts/iocsr_config.h
+++ b/board/terasic/de10-standard/qts/iocsr_config.h
@@ -6,10 +6,10 @@
 #ifndef __SOCFPGA_IOCSR_CONFIG_H__
 #define __SOCFPGA_IOCSR_CONFIG_H__
 
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH     764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH     1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH     955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH     16766
+#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH        764
+#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH        1719
+#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH        955
+#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH        16766
 
 const unsigned long iocsr_scan_chain0_table[] = {
        0x00000000,

diff --git a/board/terasic/de10-standard/qts/pll_config.h b/board/terasic/de10-standard/qts/pll_config.h
index b08a977917959ff050a567d3bf3f9ef92d48525e..c1ecd4b8208f3b9846b2c46f7d3b93321409b616 100644 (file)
--- a/board/terasic/de10-standard/qts/pll_config.h
+++ b/board/terasic/de10-standard/qts/pll_config.h
@@ -6,79 +6,79 @@
 #ifndef __SOCFPGA_PLL_CONFIG_H__
 #define __SOCFPGA_PLL_CONFIG_H__
 
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define CFG_HPS_DBCTRL_STAYOSC1 1
 
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 18
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CFG_HPS_MAINPLLGRP_VCO_NUMER 73
+#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
+#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 18
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
 
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CFG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CFG_HPS_PERPLLGRP_SRC_NAND 2
+#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
 
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
 
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 370000000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define CFG_HPS_CLK_OSC1_HZ 25000000
+#define CFG_HPS_CLK_OSC2_HZ 25000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1850000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_SDRVCO_HZ 800000000
+#define CFG_HPS_CLK_EMAC0_HZ 1953125
+#define CFG_HPS_CLK_EMAC1_HZ 250000000
+#define CFG_HPS_CLK_USBCLK_HZ 200000000
+#define CFG_HPS_CLK_NAND_HZ 50000000
+#define CFG_HPS_CLK_SDMMC_HZ 200000000
+#define CFG_HPS_CLK_QSPI_HZ 370000000
+#define CFG_HPS_CLK_SPIM_HZ 200000000
+#define CFG_HPS_CLK_CAN0_HZ 12500000
+#define CFG_HPS_CLK_CAN1_HZ 12500000
+#define CFG_HPS_CLK_GPIODB_HZ 32000
+#define CFG_HPS_CLK_L4_MP_HZ 100000000
+#define CFG_HPS_CLK_L4_SP_HZ 100000000
 
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 4
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
+#define CFG_HPS_ALTERAGRP_MPUCLK 1
+#define CFG_HPS_ALTERAGRP_MAINCLK 4
+#define CFG_HPS_ALTERAGRP_DBGATCLK 4
 
 
 #endif /* __SOCFPGA_PLL_CONFIG_H__ */

diff --git a/board/terasic/de10-standard/qts/sdram_config.h b/board/terasic/de10-standard/qts/sdram_config.h
index 630b5511a61ccba1ab60031d7bfdb2d90bd63f94..1bfa4277282d858b6cfd10aebc03d30f23099130 100644 (file)
--- a/board/terasic/de10-standard/qts/sdram_config.h
+++ b/board/terasic/de10-standard/qts/sdram_config.h
@@ -7,76 +7,76 @@
 #define __SOCFPGA_SDRAM_CONFIG_H__
 
 /* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR             0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP             0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH           0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP             0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER               0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN               0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                   0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                   8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN               1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT             10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH             2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS              3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS               10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                        1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS               15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH           8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH             32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ                    0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                   1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                  0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                 11
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                        7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                        18
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                        104
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                        3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD             6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI            3120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP              6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR              6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR             4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                        14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                        3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT         3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT                512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                        0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST                     0x1FF
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK           3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES       0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES   8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0      0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32     0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0       0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4      0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36     0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY         0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0   0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32  0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0    0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14   0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46   0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0               0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN               0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP             0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA          0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP             0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR                0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP                0xB00088
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH              0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP                0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER          0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                   0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN          0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                      0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                      8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                    2
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                   0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN          1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT                10
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH                2
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS         3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS          10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                   1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS          15
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH              8
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH                32
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                    0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ                       0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                      1
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                     0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                    11
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                   7
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                   18
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                   104
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                   3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD                6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI               3120
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP         6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR         6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR                4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                   14
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                    20
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                   3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT            3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT           512
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                    0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                   0
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST                        0x1FF
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK              3
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES  0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES      8
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32        0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0  0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36        0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY            0x3FFD1088
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0      0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32     0x1EF84
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0       0x2020
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14      0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46      0xF800
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0          0x200
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN          0
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP                0x760210
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                    2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA             0
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP                0x980543
 
 /* Sequencer auto configuration */
 #define RW_MGR_ACTIVATE_0_AND_1        0x0D

diff --git a/board/terasic/sockit/qts/iocsr_config.h b/board/terasic/sockit/qts/iocsr_config.h
index b8cb5f08ab6975f6a134619e2f853ee80ba15a90..7b72ae9c3c2cb065b6920741def1c46a6d604c2f 100644 (file)
--- a/board/terasic/sockit/qts/iocsr_config.h
+++ b/board/terasic/sockit/qts/iocsr_config.h
@@ -6,10 +6,10 @@
 #ifndef __SOCFPGA_IOCSR_CONFIG_H__
 #define __SOCFPGA_IOCSR_CONFIG_H__
 
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH     764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH     1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH     955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH     16766
+#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH        764
+#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH        1719
+#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH        955
+#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH        16766
 
 const unsigned long iocsr_scan_chain0_table[] = {
        0x00000000,

diff --git a/board/terasic/sockit/qts/pll_config.h b/board/terasic/sockit/qts/pll_config.h
index f6ffa08654adaec313bf2948980e95b382e38721..104e324d8a4fe23cdba9288f4b64ca34a1ebe5f8 100644 (file)
--- a/board/terasic/sockit/qts/pll_config.h
+++ b/board/terasic/sockit/qts/pll_config.h
@@ -6,79 +6,79 @@
 #ifndef __SOCFPGA_PLL_CONFIG_H__
 #define __SOCFPGA_PLL_CONFIG_H__
 
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define CFG_HPS_DBCTRL_STAYOSC1 1
 
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
 
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CFG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CFG_HPS_PERPLLGRP_SRC_NAND 2
+#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
 
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
 
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 400000000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define CFG_HPS_CLK_OSC1_HZ 25000000
+#define CFG_HPS_CLK_OSC2_HZ 25000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_SDRVCO_HZ 800000000
+#define CFG_HPS_CLK_EMAC0_HZ 1953125
+#define CFG_HPS_CLK_EMAC1_HZ 250000000
+#define CFG_HPS_CLK_USBCLK_HZ 200000000
+#define CFG_HPS_CLK_NAND_HZ 50000000
+#define CFG_HPS_CLK_SDMMC_HZ 200000000
+#define CFG_HPS_CLK_QSPI_HZ 400000000
+#define CFG_HPS_CLK_SPIM_HZ 200000000
+#define CFG_HPS_CLK_CAN0_HZ 12500000
+#define CFG_HPS_CLK_CAN1_HZ 12500000
+#define CFG_HPS_CLK_GPIODB_HZ 32000
+#define CFG_HPS_CLK_L4_MP_HZ 100000000
+#define CFG_HPS_CLK_L4_SP_HZ 100000000
 
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define CFG_HPS_ALTERAGRP_MPUCLK 1
+#define CFG_HPS_ALTERAGRP_MAINCLK 3
+#define CFG_HPS_ALTERAGRP_DBGATCLK 3
 
 
 #endif /* __SOCFPGA_PLL_CONFIG_H__ */

diff --git a/board/terasic/sockit/qts/sdram_config.h b/board/terasic/sockit/qts/sdram_config.h
index 96cc35703413f5d6e7c2ce08e5e8e80dfda4ab23..efdbc8557408163f54a2097d4ec1b213d6324070 100644 (file)
--- a/board/terasic/sockit/qts/sdram_config.h
+++ b/board/terasic/sockit/qts/sdram_config.h
@@ -7,76 +7,76 @@
 #define __SOCFPGA_SDRAM_CONFIG_H__
 
 /* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR             0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP             0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH           0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP             0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER               0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN               0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                   0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                   8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN               1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT             10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH             2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS              3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS               10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                        1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS               15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH           8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH             32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ                    0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                   1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                  0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                 11
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                        8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                        12
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                        104
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                        3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD             6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI            3120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP              6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR              6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR             4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                        14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                        3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT         3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT                512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                        0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST                     0x1FF
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK           3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES       0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES   8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0      0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32     0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0       0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4      0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36     0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY         0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0        0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32       0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64       0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0   0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32  0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0    0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14   0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46   0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0               0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN               0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP             0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA          0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP             0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR                0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP                0xB00088
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH              0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP                0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER          0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                   0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN          0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                      0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                      8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                    2
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                   0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN          1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT                10
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH                2
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS         3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS          10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                   1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS          15
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH              8
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH                32
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                    0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ                       0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                      1
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                     0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                    11
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                   8
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                   12
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                   104
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                   3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD                6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI               3120
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP         6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR         6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR                4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                   4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                   14
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                    20
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                   3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT            3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT           512
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                    0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                   0
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST                        0x1FF
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK              3
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES  0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES      8
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32        0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0  0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36        0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY            0x3FFD1088
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0   0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32  0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64  0x0101
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0      0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32     0x1EF84
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0       0x2020
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14      0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46      0xF800
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0          0x200
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN          0
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP                0x760210
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                    2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA             0
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP                0x980543
 
 /* Sequencer auto configuration */
 #define RW_MGR_ACTIVATE_0_AND_1        0x0D