arm: dts: k3-j7200-common-proc-board: Enable SERDES DT

Add default lane function for torrent serdes. This is in sync
with v5.13 Linux Kernel.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-14-kishon@ti.com

diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts b/arch/arm/dts/k3-j7200-common-proc-board.dts
index 5120711d4fef4bb4fd20d4d047eb2af733f52eb0..f0440cda1a71ecc5c45e3ac11ff78e5feebb68f3 100644 (file)
--- a/arch/arm/dts/k3-j7200-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-common-proc-board.dts
@@ -9,6 +9,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/net/ti-dp83867.h>
 #include <dt-bindings/mux/ti-serdes.h>
+#include <dt-bindings/phy/phy.h>
 
 / {
        chosen {
@@ -281,3 +282,25 @@
                ti,adc-channels = <0 1 2 3 4 5 6 7>;
        };
 };
+
+&serdes_refclk {
+       clock-frequency = <100000000>;
+};
+
+&serdes0 {
+       serdes0_pcie_link: link@0 {
+               reg = <0>;
+               cdns,num-lanes = <2>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_PCIE>;
+               resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
+       };
+
+       serdes0_qsgmii_link: link@1 {
+               reg = <2>;
+               cdns,num-lanes = <1>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_QSGMII>;
+               resets = <&serdes_wiz0 3>;
+       };
+};