arm: vf610: Add QSPI support for VF610TWR

Add QSPI support for VF610TWR, such as clock and iomux.

Signed-off-by: Alison Wang <Huan.Wang@freescale.com>
Signed-off-by: Chao Fu <b44548@freescale.com>

diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h
index e17c7d1f7042f138ac41acb48eb100ebd02953e5..5256624adf4691c33d68395faef0ab06594de7fc 100644 (file)
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -150,6 +150,9 @@ struct anadig_reg {
 #define CCM_CACRR_ARM_CLK_DIV_MASK             0x7
 #define CCM_CACRR_ARM_CLK_DIV(v)               ((v) & 0x7)
 
+#define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET                22
+#define CCM_CSCMR1_QSPI0_CLK_SEL_MASK          (0x3 << 22)
+#define CCM_CSCMR1_QSPI0_CLK_SEL(v)            (((v) & 0x3) << 22)
 #define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET       18
 #define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK         (0x3 << 18)
 #define CCM_CSCMR1_ESDHC1_CLK_SEL(v)           (((v) & 0x3) << 18)
@@ -161,6 +164,11 @@ struct anadig_reg {
 #define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK         (0xf << 20)
 #define CCM_CSCDR2_ESDHC1_CLK_DIV(v)           (((v) & 0xf) << 20)
 
+#define CCM_CSCDR3_QSPI0_EN                    (1 << 4)
+#define CCM_CSCDR3_QSPI0_DIV(v)                        ((v) << 3)
+#define CCM_CSCDR3_QSPI0_X2_DIV(v)             ((v) << 2)
+#define CCM_CSCDR3_QSPI0_X4_DIV(v)             ((v) & 0x3)
+
 #define CCM_CSCMR2_RMII_CLK_SEL_OFFSET         4
 #define CCM_CSCMR2_RMII_CLK_SEL_MASK           (0x3 << 4)
 #define CCM_CSCMR2_RMII_CLK_SEL(v)             (((v) & 0x3) << 4)
@@ -170,6 +178,7 @@ struct anadig_reg {
 #define CCM_CCGR0_UART1_CTRL_MASK              (0x3 << 16)
 #define CCM_CCGR1_PIT_CTRL_MASK                        (0x3 << 14)
 #define CCM_CCGR1_WDOGA5_CTRL_MASK             (0x3 << 28)
+#define CCM_CCGR2_QSPI0_CTRL_MASK              (0x3 << 8)
 #define CCM_CCGR2_IOMUXC_CTRL_MASK             (0x3 << 16)
 #define CCM_CCGR2_PORTA_CTRL_MASK              (0x3 << 18)
 #define CCM_CCGR2_PORTB_CTRL_MASK              (0x3 << 20)

diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 0c28e1b8403a4f52a89c1e26117ea5a558323b23..bd6f680b63baaa00ffb01b27291f38461494441f 100644 (file)
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -87,6 +87,8 @@
 #define ENET_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00050000)
 #define ENET1_BASE_ADDR                (AIPS1_BASE_ADDR + 0x00051000)
 
+#define QSPI0_AMBA_BASE                0x20000000
+
 /* MUX mode and PAD ctrl are in one register */
 #define CONFIG_IOMUX_SHARE_CONF_REG
 

diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
index 88807d8db47355e35b389c0e6db789818f711e5f..a9656416815768f4183e623705da162572054040 100644 (file)
--- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h
+++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -20,6 +20,9 @@
 #define VF610_I2C_PAD_CTRL     (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
                                PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE)
 
+#define VF610_QSPI_PAD_CTRL    (PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_150ohm | \
+                               PAD_CTL_PUS_22K_UP | PAD_CTL_OBE_IBE_ENABLE)
+
 enum {
        VF610_PAD_PTA6__RMII0_CLKIN             = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),
        VF610_PAD_PTA6__RMII0_CLKOUT            = IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
@@ -53,6 +56,18 @@ enum {
        VF610_PAD_PTA29__ESDHC1_DAT3            = IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
        VF610_PAD_PTB14__I2C0_SCL               = IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL),
        VF610_PAD_PTB15__I2C0_SDA               = IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL),
+       VF610_PAD_PTD0__QSPI0_A_QSCK            = IOMUX_PAD(0x013c, 0x013c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+       VF610_PAD_PTD1__QSPI0_A_CS0             = IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+       VF610_PAD_PTD2__QSPI0_A_DATA3           = IOMUX_PAD(0x0144, 0x0144, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+       VF610_PAD_PTD3__QSPI0_A_DATA2           = IOMUX_PAD(0x0148, 0x0148, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+       VF610_PAD_PTD4__QSPI0_A_DATA1           = IOMUX_PAD(0x014c, 0x014c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+       VF610_PAD_PTD5__QSPI0_A_DATA0           = IOMUX_PAD(0x0150, 0x0150, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+       VF610_PAD_PTD7__QSPI0_B_QSCK            = IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+       VF610_PAD_PTD8__QSPI0_B_CS0             = IOMUX_PAD(0x015c, 0x015c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+       VF610_PAD_PTD9__QSPI0_B_DATA3           = IOMUX_PAD(0x0160, 0x0160, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+       VF610_PAD_PTD10__QSPI0_B_DATA2          = IOMUX_PAD(0x0164, 0x0164, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+       VF610_PAD_PTD11__QSPI0_B_DATA1          = IOMUX_PAD(0x0168, 0x0168, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+       VF610_PAD_PTD12__QSPI0_B_DATA0          = IOMUX_PAD(0x016c, 0x016c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
        VF610_PAD_DDR_A15__DDR_A_15             = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
        VF610_PAD_DDR_A14__DDR_A_14             = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
        VF610_PAD_DDR_A13__DDR_A_13             = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL),

diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c
index d64d3aa872205f237fce290ae4ec0187c1ead705..54a9f2c7c35d122a050e3f67b41be7dd4b052b24 100644 (file)
--- a/board/freescale/vf610twr/vf610twr.c
+++ b/board/freescale/vf610twr/vf610twr.c
@@ -278,6 +278,26 @@ static void setup_iomux_i2c(void)
        imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
 }
 
+static void setup_iomux_qspi(void)
+{
+       static const iomux_v3_cfg_t qspi0_pads[] = {
+               VF610_PAD_PTD0__QSPI0_A_QSCK,
+               VF610_PAD_PTD1__QSPI0_A_CS0,
+               VF610_PAD_PTD2__QSPI0_A_DATA3,
+               VF610_PAD_PTD3__QSPI0_A_DATA2,
+               VF610_PAD_PTD4__QSPI0_A_DATA1,
+               VF610_PAD_PTD5__QSPI0_A_DATA0,
+               VF610_PAD_PTD7__QSPI0_B_QSCK,
+               VF610_PAD_PTD8__QSPI0_B_CS0,
+               VF610_PAD_PTD9__QSPI0_B_DATA3,
+               VF610_PAD_PTD10__QSPI0_B_DATA2,
+               VF610_PAD_PTD11__QSPI0_B_DATA1,
+               VF610_PAD_PTD12__QSPI0_B_DATA0,
+       };
+
+       imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads));
+}
+
 #ifdef CONFIG_FSL_ESDHC
 struct fsl_esdhc_cfg esdhc_cfg[1] = {
        {ESDHC1_BASE_ADDR},
@@ -321,7 +341,8 @@ static void clock_init(void)
        clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
                CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
                CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
-               CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
+               CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
+               CCM_CCGR2_QSPI0_CTRL_MASK);
        clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
                CCM_CCGR3_ANADIG_CTRL_MASK);
        clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
@@ -352,11 +373,14 @@ static void clock_init(void)
                CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
                CCM_CACRR_ARM_CLK_DIV(0));
        clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
-               CCM_CSCMR1_ESDHC1_CLK_SEL(3));
+               CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3));
        clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
                CCM_CSCDR1_RMII_CLK_EN);
        clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
                CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0));
+       clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
+               CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
+               CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3));
        clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
                CCM_CSCMR2_RMII_CLK_SEL(0));
 }
@@ -386,6 +410,7 @@ int board_early_init_f(void)
        setup_iomux_uart();
        setup_iomux_enet();
        setup_iomux_i2c();
+       setup_iomux_qspi();
 
        return 0;
 }

diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index 500fd2fd6135086320f78bbced1fa86862a501ce..034255041226079f5078e6f2d16d6f502c08eab0 100644 (file)
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -68,6 +68,18 @@
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_MICREL
 
+/* QSPI Configs*/
+#define CONFIG_FSL_QSPI
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE            (1 << 24)
+#define FSL_QSPI_FLASH_NUM             2
+#define CONFIG_SYS_FSL_QSPI_LE
+#endif
+
 /* I2C Configs */
 #define CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C