x86: sandbox: pch: Add a CONFIG option for PCH

At present this uclass is selected only on x86. In order to add a test for
it, it must also support sandbox. Create a new CONFIG_PCH option and
enable it on x86 and sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/Kconfig b/arch/Kconfig
index 35e2712fce927f3d8d8e04ab9ba20591dc006ea4..d9afe269f20a294ce3a6440252b836be0ab724b7 100644 (file)
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -117,6 +117,7 @@ config SANDBOX
        imply VIRTIO_BLK
        imply VIRTIO_NET
        imply DM_SOUND
+       imply PCH
 
 config SH
        bool "SuperH architecture"
@@ -160,6 +161,7 @@ config X86
        imply USB_ETHER_ASIX
        imply USB_ETHER_SMSC95XX
        imply USB_HOST_ETHER
+       imply PCH
 
 config XTENSA
        bool "Xtensa architecture"

diff --git a/drivers/Kconfig b/drivers/Kconfig
index e9fbadd13d5a6eb3284dcc3adf1e6ac5549d2260..f24351ac4f1d2d5e72a9dbfad86f15aa7eb608ec 100644 (file)
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -64,6 +64,8 @@ source "drivers/nvme/Kconfig"
 
 source "drivers/pci/Kconfig"
 
+source "drivers/pch/Kconfig"
+
 source "drivers/pcmcia/Kconfig"
 
 source "drivers/phy/Kconfig"

diff --git a/drivers/Makefile b/drivers/Makefile
index eca023ac04da848c090c1b6257f2aec83996acc8..a7bba3ed564b0dfc4035be3254a81abd1612a9f0 100644 (file)
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -86,7 +86,8 @@ obj-y += misc/
 obj-$(CONFIG_MMC) += mmc/
 obj-$(CONFIG_NVME) += nvme/
 obj-y += pcmcia/
-obj-$(CONFIG_X86) += pch/
+obj-y += dfu/
+obj-$(CONFIG_PCH) += pch/
 obj-y += phy/allwinner/
 obj-y += phy/marvell/
 obj-y += rtc/

diff --git a/drivers/pch/Kconfig b/drivers/pch/Kconfig
new file mode 100644 (file)
index 0000000..18f006d
--- /dev/null
+++ b/drivers/pch/Kconfig
@@ -0,0 +1,9 @@
+config PCH
+       bool "Enable Platform-controller Hub (PCH) support"
+       depends on X86 || SANDBOX
+       help
+         Most x86 chips include a PCH which is responsible for handling
+         parts of the system not handled by that CPU. It supersedes the
+         northbridge / southbridge architecture that was previously used. The
+         PCH allows for higher performance since the memory functions are
+         handled in the CPU.