ppc4xx: Fix build problems of IBM DDR2 NAND booting targets

This change is needed to compile the PPC4xx NAND booting targets
equipped with the IBM DDR2 SDRAM controller.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Stefan Roese <sr@denx.de>

diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index faa3720df3f5f67d0f7365b2a522390320a8fe60..80e2739fe011218e7c09fda94e617c3cdf7971b0 100644 (file)
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -363,18 +363,6 @@ int checkboard(void)
 }
 #endif /* !defined(CONFIG_ARCHES) */
 
-#if defined(CONFIG_NAND_U_BOOT)
-/*
- * NAND booting U-Boot version uses a fixed initialization, since the whole
- * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
- * code.
- */
-phys_size_t initdram(int board_type)
-{
-       return CONFIG_SYS_MBYTES_SDRAM << 20;
-}
-#endif
-
 #if defined(CONFIG_PCI)
 int board_pcie_first(void)
 {