CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_CLK_CCF=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_IPROC=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_TFTP_TSIZE=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_OCTEONTX=y
CONFIG_MTD=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_OCTEONTX=y
CONFIG_MTD=y
CONFIG_AHCI_PCI=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OCTEONTX=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_AHCI_PCI=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OCTEONTX=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_MXC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
CONFIG_FASTBOOT_BUF_SIZE=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_SYS_I2C_MXC=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5b010000
#define USDHC2_BASE_ADDR 0x5b020000
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
/* Networking */
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5b010000
#define USDHC2_BASE_ADDR 0x5b020000
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_SYS_BOOTM_LEN 0x01800000
/* Access eMMC Boot_1 and Boot_2 partitions */
-#define CONFIG_SUPPORT_EMMC_BOOT
/* enable 64-bit PCI resources */
#define CONFIG_SYS_PCI_64BIT 1
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
#define USDHC3_BASE_ADDR 0x5B030000
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5b010000
#define USDHC2_BASE_ADDR 0x5b020000
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_NETMASK 255.255.255.0
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
-#define CONFIG_SUPPORT_EMMC_BOOT
/* I2C configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#ifdef CONFIG_AHAB_BOOT
#define AHAB_ENV "sec_boot=yes\0"
#define USDHC2_BASE_ADDR 0x5B020000
#define USDHC3_BASE_ADDR 0x5B030000
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
-
/* FUSE command */
/* Boot M4 */
#if defined(CONFIG_MMC_OCTEONTX)
#define MMC_SUPPORTS_TUNING
/** EMMC specific defines */
-#define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_SUPPORT_EMMC_RPMB
#endif
/** EMMC specific defines */
#if defined(CONFIG_MMC_OCTEONTX)
-#define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_SUPPORT_EMMC_RPMB
#endif
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
-#define CONFIG_SUPPORT_EMMC_BOOT
/* I2C configs */
/* MMC Configuration */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
-#define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
/* USB Configs */